{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:43:45Z","timestamp":1750308225933,"version":"3.41.0"},"reference-count":18,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2005,3,1]],"date-time":"2005-03-01T00:00:00Z","timestamp":1109635200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGARCH Comput. Archit. News"],"published-print":{"date-parts":[[2005,3]]},"abstract":"<jats:p>\n            The increasing need for security has caused system designers to consider placing some security support directly at the hardware level. In fact, this is starting to emerge as an important consideration in processor design, because the performance overhead of supporting security in hardware is usually significantly lower than a complete software solution. In this paper, we investigate integrating some security support into hardware. We show that security support can be added at some acceptable cost in area and performance. We propose a processor extension called ChipLock. It provides hardware security support for a mostly untrusted operating system to ensure the integrity and confidentiality of all computational results. ChipLock's modular design can be easily integrated into existing hardware platforms with only slight modification to the operating system. ChipLock includes a built-in hardware Key Manager that supports symmetric key assignment, and a read-only-memory, TrustROM, that executes secure hardware routines. The software required is a small trusted portion of the operating system called Trust-Code. We modeled ChipLock's architecture on a full system simulator and showed that, for SPEC2000 benchmarks, it adds about an average of 20% to the execution time, primarily from cryptographic and verification latencies. In addition, layout studies show an area cost of about 8 mm\n            <jats:sup>2<\/jats:sup>\n            in 180 nm technology. This translates to an area overhead of 5% ~ 15% depending on the processor type.\n          <\/jats:p>","DOI":"10.1145\/1055626.1055644","type":"journal-article","created":{"date-parts":[[2005,11,7]],"date-time":"2005-11-07T19:28:32Z","timestamp":1131391712000},"page":"134-143","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":15,"title":["ChipLock"],"prefix":"10.1145","volume":"33","author":[{"given":"Taeho","family":"Kgil","sequence":"first","affiliation":[{"name":"University of Michigan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Laura","family":"Falk","sequence":"additional","affiliation":[{"name":"University of Michigan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Trevor","family":"Mudge","sequence":"additional","affiliation":[{"name":"University of Michigan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2005,3]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.5555\/956417.956575"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379237"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/945445.945463"},{"key":"e_1_2_1_4_1","unstructured":"TCPA Alliance http:\/\/www.trustedcomputing.org\/  TCPA Alliance http:\/\/www.trustedcomputing.org\/"},{"key":"e_1_2_1_5_1","unstructured":"Advanced Encryption Standard (AES) {FIPS 197}  Advanced Encryption Standard (AES) {FIPS 197}"},{"key":"e_1_2_1_6_1","first-page":"29","volume-title":"The Second USENIX Workshop on Electronic Commerce Proceedings, USENIX Press","author":"Wagner D.","year":"1996"},{"key":"e_1_2_1_7_1","unstructured":"N. Binkert E. Hallnor and S. Reinhardt. Network-Oriented Full-System Simulation using M5 Sixth Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW) February 2003  N. Binkert E. Hallnor and S. Reinhardt. Network-Oriented Full-System Simulation using M5 Sixth Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW) February 2003"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.982917"},{"key":"e_1_2_1_9_1","first-page":"595","volume-title":"ESSCIRC 2002. Proceedings of the 28th European Solid-State Circuit Conference","author":"Kinniment D.","year":"2002"},{"key":"e_1_2_1_10_1","unstructured":"MD5 http:\/\/www.sci-worx.com\/internet\/designobjects\/do_list\/handouts\/cryptography\/VC01C2.008\/VC01C2.008HO.pdf  MD5 http:\/\/www.sci-worx.com\/internet\/designobjects\/do_list\/handouts\/cryptography\/VC01C2.008\/VC01C2.008HO.pdf"},{"key":"e_1_2_1_11_1","unstructured":"RSA http:\/\/www.sci-worx.com\/internet\/homepage_internet_e.html?\/internet\/designobjects\/do_list\/handouts\/cryptography\/VC01C2.002\/rsa.htm  RSA http:\/\/www.sci-worx.com\/internet\/homepage_internet_e.html?\/internet\/designobjects\/do_list\/handouts\/cryptography\/ VC01C2.002\/rsa.htm"},{"key":"e_1_2_1_12_1","unstructured":"OPENCORES.ORG http:\/\/www.opencores.org  OPENCORES.ORG http:\/\/www.opencores.org"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379268"},{"key":"e_1_2_1_14_1","unstructured":"The MOSIS Service http:\/\/www.mosis.org  The MOSIS Service http:\/\/www.mosis.org"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.966495"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/586110.586132"},{"volume-title":"Certifying Program Execution with Secure Processors. 9th Workshop on Hot Topics in Operating Systems (HotOS IX)","year":"2003","author":"Chen B.","key":"e_1_2_1_17_1"},{"volume-title":"Self-Securing Storage: Protecting Data in Compromised Systems. Appears in Proc. of the 4th Symposium on Operating Systems Design and Implementation","year":"2000","author":"Strunk J.","key":"e_1_2_1_18_1"}],"container-title":["ACM SIGARCH Computer Architecture News"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1055626.1055644","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1055626.1055644","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T16:31:27Z","timestamp":1750264287000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1055626.1055644"}},"subtitle":["support for secure microarchitectures"],"short-title":[],"issued":{"date-parts":[[2005,3]]},"references-count":18,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2005,3]]}},"alternative-id":["10.1145\/1055626.1055644"],"URL":"https:\/\/doi.org\/10.1145\/1055626.1055644","relation":{},"ISSN":["0163-5964"],"issn-type":[{"type":"print","value":"0163-5964"}],"subject":[],"published":{"date-parts":[[2005,3]]},"assertion":[{"value":"2005-03-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}