{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,7]],"date-time":"2026-03-07T18:14:51Z","timestamp":1772907291802,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":24,"publisher":"ACM","license":[{"start":{"date-parts":[[2005,4,17]],"date-time":"2005-04-17T00:00:00Z","timestamp":1113696000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2005,4,17]]},"DOI":"10.1145\/1057661.1057675","type":"proceedings-article","created":{"date-parts":[[2005,8,3]],"date-time":"2005-08-03T08:31:47Z","timestamp":1123057907000},"page":"50-55","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["A unified processor architecture for RISC & VLIW DSP"],"prefix":"10.1145","author":[{"given":"Tay-Jyi","family":"Lin","sequence":"first","affiliation":[{"name":"National Chiao Tung University, Taiwan"}]},{"given":"Chie-Min","family":"Chao","sequence":"additional","affiliation":[{"name":"National Chiao Tung University, Taiwan"}]},{"given":"Chia-Hsien","family":"Liu","sequence":"additional","affiliation":[{"name":"National Chiao Tung University, Taiwan"}]},{"given":"Pi-Chen","family":"Hsiao","sequence":"additional","affiliation":[{"name":"National Chiao Tung University, Taiwan"}]},{"given":"Shin-Kai","family":"Chen","sequence":"additional","affiliation":[{"name":"National Chiao Tung University, Taiwan"}]},{"given":"Li-Chun","family":"Lin","sequence":"additional","affiliation":[{"name":"National Chiao Tung University, Taiwan"}]},{"given":"Chih-Wei","family":"Liu","sequence":"additional","affiliation":[{"name":"National Chiao Tung University, Taiwan"}]},{"given":"Chein-Wei","family":"Jen","sequence":"additional","affiliation":[{"name":"National Chiao Tung University, Taiwan"}]}],"member":"320","published-online":{"date-parts":[[2005,4,17]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Intel PXA800F Cellular Processor - Development Manual Intel Corp. Feb. 2003.  Intel PXA800F Cellular Processor - Development Manual Intel Corp. Feb. 2003."},{"key":"e_1_3_2_1_2_1","volume-title":"Jan.","author":"Dual Core 0","year":"2003","unstructured":"OMAP591 0 Dual Core Processor - Technical Reference Manual , Texas Instruments , Jan. 2003 . OMAP5910 Dual Core Processor - Technical Reference Manual, Texas Instruments, Jan. 2003."},{"key":"e_1_3_2_1_3_1","first-page":"03","article-title":"ARM picks up performance","volume":"4","author":"Levy M.","unstructured":"M. Levy , \" ARM picks up performance ,\" Microprocessor Report , 4\/7 \/ 03 - 01 . M. Levy, \"ARM picks up performance,\" Microprocessor Report, 4\/7\/03-01.","journal-title":"Microprocessor Report"},{"key":"e_1_3_2_1_4_1","unstructured":"R. A. Quinnell \"Logical combination? Convergence products need both RISC and DSP processors but merging them may not be the answer \" EDN 1\/23\/2003.  R. A. Quinnell \"Logical combination? Convergence products need both RISC and DSP processors but merging them may not be the answer \" EDN 1\/23\/2003."},{"key":"e_1_3_2_1_5_1","volume-title":"Computer Architecture - A Quantitative Approach","author":"Hennessy J. L","year":"2002","unstructured":"J. L Hennessy , and D. A. Patterson , Computer Architecture - A Quantitative Approach , 3 rd Edition, Morgan Kaufmann , 2002 . J. L Hennessy, and D. A. Patterson, Computer Architecture - A Quantitative Approach, 3rd Edition, Morgan Kaufmann, 2002.","edition":"3"},{"key":"e_1_3_2_1_6_1","first-page":"375","article-title":"Register organization for media processing","author":"Rixner S.","year":"2000","unstructured":"S. Rixner , W. J. Dally , B. Khailany , P. Mattson , U. J. Kapasi , and J. D. Owens , \" Register organization for media processing ,\" in Proc. HPCA-6 , 2000 , pp. 375 -- 386 . S. Rixner, W. J. Dally, B. Khailany, P. Mattson, U. J. Kapasi, and J. D. Owens, \"Register organization for media processing,\" in Proc. HPCA-6, 2000, pp.375--386.","journal-title":"Proc. HPCA-6"},{"key":"e_1_3_2_1_7_1","first-page":"77","volume-title":"IPDPS","author":"Zalamea J.","year":"2003","unstructured":"J. Zalamea , J. Llosa , E. Ayguade , and M. Valero , \" Hierarchical clustered register file organization for VLIW processors,\" in Proc . IPDPS , 2003 , pp. 77 -- 86 . J. Zalamea, J. Llosa, E. Ayguade, and M. Valero, \"Hierarchical clustered register file organization for VLIW processors,\" in Proc. IPDPS, 2003, pp.77--86."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339682"},{"key":"e_1_3_2_1_9_1","volume-title":"WO 00\/54144","author":"Barry E. F.","year":"2000","unstructured":"E. F. Barry , G. G. Pechanek , and P. R. Marchand , \" Register file indexing methods and apparatus for providing indirect control of register file addressing in a VLIW processor,\" International Application Published under the Patent Cooperation Treaty (PCT) , WO 00\/54144 , Mar. 9 2000 . E. F. Barry, G. G. Pechanek, and P. R. Marchand, \"Register file indexing methods and apparatus for providing indirect control of register file addressing in a VLIW processor,\" International Application Published under the Patent Cooperation Treaty (PCT), WO 00\/54144, Mar. 9 2000."},{"key":"e_1_3_2_1_10_1","volume-title":"Apr","author":"Library Programmer's Reference DSP","year":"2002","unstructured":"TMS320C64x DSP Library Programmer's Reference , Texas Instruments Inc ., Apr 2002 . TMS320C64x DSP Library Programmer's Reference, Texas Instruments Inc., Apr 2002."},{"key":"e_1_3_2_1_11_1","first-page":"629","article-title":"Copied register files for data processors having many execution units","volume":"6","author":"Arora K.","year":"2003","unstructured":"K. Arora , H. Sharangpani , and R. Gupta , \" Copied register files for data processors having many execution units \" U.S. Patent 6 , 629 ,232, Sep. 30, 2003 . K. Arora, H. Sharangpani, and R. Gupta, \"Copied register files for data processors having many execution units\" U.S. Patent 6,629,232, Sep. 30, 2003.","journal-title":"U.S. Patent"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.962280"},{"key":"e_1_3_2_1_13_1","first-page":"354","article-title":"Inter-cluster communication models for clustered VLIW processors","author":"Terechko A.","year":"2003","unstructured":"A. Terechko , E. L. Thenaff , M. Garg , J. Eijndhoven , and H. Corp oraal , \" Inter-cluster communication models for clustered VLIW processors ,\" in Proc. HPCA-9 , 2003 , pp. 354 -- 364 . A. Terechko, E. L. Thenaff, M. Garg, J. Eijndhoven, and H. Corporaal, \"Inter-cluster communication models for clustered VLIW processors,\" in Proc. HPCA-9, 2003, pp.354--364.","journal-title":"Proc. HPCA-9"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/502217.502244"},{"key":"e_1_3_2_1_15_1","first-page":"348","article-title":"The ManArray embedded processor architecture","volume":"1","author":"Pechanek G. G.","year":"2000","unstructured":"G. G. Pechanek and S. Vassiliadis , \" The ManArray embedded processor architecture ,\" Euromicro Conf. , vol. 1 , pp. 348 -- 355 , Sep. , 2000 . G. G. Pechanek and S. Vassiliadis, \"The ManArray embedded processor architecture,\" Euromicro Conf., vol.1, pp.348--355, Sep., 2000.","journal-title":"Euromicro Conf."},{"key":"e_1_3_2_1_16_1","volume-title":"May","author":"Fettweis G.","year":"2002","unstructured":"G. Fettweis , M. Bolle , J. Kneip , and M. Weiss , \" OnDSP: a new architecture for wireless LAN applications,\" Embedded Processor Forum , May 2002 . G. Fettweis, M. Bolle, J. Kneip, and M. Weiss, \"OnDSP: a new architecture for wireless LAN applications,\" Embedded Processor Forum, May 2002."},{"key":"e_1_3_2_1_17_1","volume-title":"July","author":"Programmer's Guide DSP","year":"2000","unstructured":"TMS320C55x DSP Programmer's Guide , Texas Instruments Inc ., July 2000 . TMS320C55x DSP Programmer's Guide, Texas Instruments Inc., July 2000."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/MSP.2002.1012346"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2001.941089"},{"key":"e_1_3_2_1_20_1","volume-title":"JPEG - Still Image Data Compression Standard","author":"Pennebaker W. B.","year":"1993","unstructured":"W. B. Pennebaker and J. L. Mitchell , JPEG - Still Image Data Compression Standard , Van Nostrand Reinhold , 1993 . W. B. Pennebaker and J. L. Mitchell, JPEG - Still Image Data Compression Standard, Van Nostrand Reinhold, 1993."},{"key":"e_1_3_2_1_21_1","volume-title":"ICCD","author":"Lin T. J.","year":"2003","unstructured":"T. J. Lin , C. C. Chang , C. C. Lee , and C. W. Jen , \" An efficient VLIW DSP architecture for baseband processing,\" in Proc . ICCD , 2003 . T. J. Lin, C. C. Chang, C. C. Lee, and C. W. Jen, \"An efficient VLIW DSP architecture for baseband processing,\" in Proc. ICCD, 2003."},{"key":"e_1_3_2_1_22_1","volume-title":"DSP Processor Fundamentals - Architectures and Features","author":"Lapsley P.","year":"1996","unstructured":"P. Lapsley , J. Bier , A. Shoham , and E. A. Lee , DSP Processor Fundamentals - Architectures and Features , IEEE Press , 1996 . P. Lapsley, J. Bier, A. Shoham, and E. A. Lee, DSP Processor Fundamentals - Architectures and Features, IEEE Press, 1996."},{"key":"e_1_3_2_1_23_1","volume-title":"June","author":"Architecture Manual 0","year":"2003","unstructured":"TriCore 2-32-bit Unified Processor Core v.2. 0 Architecture - Architecture Manual , Infineon Technology , June 2003 . TriCore 2-32-bit Unified Processor Core v.2.0 Architecture - Architecture Manual, Infineon Technology, June 2003."},{"key":"e_1_3_2_1_24_1","volume-title":"Programmable Digital Signal Processors - Architecture, Programming, and Applications","author":"Hu Y. H.","year":"2002","unstructured":"Y. H. Hu , Programmable Digital Signal Processors - Architecture, Programming, and Applications , Marcel Dekker Inc ., 2002 . Y. H. Hu, Programmable Digital Signal Processors - Architecture, Programming, and Applications, Marcel Dekker Inc., 2002."}],"event":{"name":"GLSVLSI05: Great Lakes Symposium on VLSI 2005","location":"Chicago Illinois USA","acronym":"GLSVLSI05","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the 15th ACM Great Lakes symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1057661.1057675","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1057661.1057675","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T21:25:59Z","timestamp":1750281959000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1057661.1057675"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005,4,17]]},"references-count":24,"alternative-id":["10.1145\/1057661.1057675","10.1145\/1057661"],"URL":"https:\/\/doi.org\/10.1145\/1057661.1057675","relation":{},"subject":[],"published":{"date-parts":[[2005,4,17]]},"assertion":[{"value":"2005-04-17","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}