{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:54:59Z","timestamp":1750308899607,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":8,"publisher":"ACM","license":[{"start":{"date-parts":[[2005,4,17]],"date-time":"2005-04-17T00:00:00Z","timestamp":1113696000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2005,4,17]]},"DOI":"10.1145\/1057661.1057687","type":"proceedings-article","created":{"date-parts":[[2005,8,3]],"date-time":"2005-08-03T08:31:47Z","timestamp":1123057907000},"page":"102-107","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["On equivalence checking and logic synthesis of circuits with a common specification"],"prefix":"10.1145","author":[{"given":"Eugene","family":"Goldberg","sequence":"first","affiliation":[{"name":"Cadence Berkeley Labs, Berkeley, CA"}]}],"member":"320","published-online":{"date-parts":[[2005,4,17]]},"reference":[{"first-page":"456","volume-title":"ICCAD-89","author":"Berman C.L.","key":"e_1_3_2_1_1_1"},{"first-page":"534","volume-title":"ICCAD-93","author":"Brand D.","key":"e_1_3_2_1_2_1"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/288548.289088"},{"key":"e_1_3_2_1_4_1","unstructured":"Goldberg E. Equivalence Checking of Dissimilar Circuits II. Technical report. CDNL-TR-2004-0830 August 2004 available at http:\/\/eigold.tripod.com\/papers.html  Goldberg E. Equivalence Checking of Dissimilar Circuits II. Technical report. CDNL-TR-2004-0830 August 2004 available at http:\/\/eigold.tripod.com\/papers.html"},{"key":"e_1_3_2_1_5_1","unstructured":"Goldberg E. Equivalence checking and logic synthesis of circuits with a common specification. Technical report. CDNL-TR-2004--1220 August 2004.  Goldberg E. Equivalence checking and logic synthesis of circuits with a common specification. Technical report. CDNL-TR-2004--1220 August 2004."},{"key":"e_1_3_2_1_6_1","unstructured":"Goldberg E. and Novikov Y. Equivalence Checking of Dissimilar Circuits IWLS-2003. May 28-30 USA. Available at http:\/\/eigold.tripod.com\/papers\/dissim-iwls.zip  Goldberg E. and Novikov Y. Equivalence Checking of Dissimilar Circuits IWLS-2003. May 28-30 USA. Available at http:\/\/eigold.tripod.com\/papers\/dissim-iwls.zip"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.5555\/645903.672929"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/266021.266090"}],"event":{"name":"GLSVLSI05: Great Lakes Symposium on VLSI 2005","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"],"location":"Chicago Illinois USA","acronym":"GLSVLSI05"},"container-title":["Proceedings of the 15th ACM Great Lakes symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1057661.1057687","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1057661.1057687","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T21:25:59Z","timestamp":1750281959000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1057661.1057687"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005,4,17]]},"references-count":8,"alternative-id":["10.1145\/1057661.1057687","10.1145\/1057661"],"URL":"https:\/\/doi.org\/10.1145\/1057661.1057687","relation":{},"subject":[],"published":{"date-parts":[[2005,4,17]]},"assertion":[{"value":"2005-04-17","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}