{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:54:59Z","timestamp":1750308899747,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":9,"publisher":"ACM","license":[{"start":{"date-parts":[[2005,4,17]],"date-time":"2005-04-17T00:00:00Z","timestamp":1113696000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2005,4,17]]},"DOI":"10.1145\/1057661.1057690","type":"proceedings-article","created":{"date-parts":[[2005,8,3]],"date-time":"2005-08-03T08:31:47Z","timestamp":1123057907000},"page":"116-121","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Area-efficient two-dimensional architectures for finite field inversion and division"],"prefix":"10.1145","author":[{"given":"Zhiyuan","family":"Yan","sequence":"first","affiliation":[{"name":"Lehigh University, Bethlehem, PA"}]},{"given":"Dilip V.","family":"Sarwate","sequence":"additional","affiliation":[{"name":"University of Illinois at Urbana-Champaign, Urbana, IL"}]}],"member":"320","published-online":{"date-parts":[[2005,4,17]]},"reference":[{"issue":"11","key":"e_1_3_2_1_1_1","first-page":"1230","article-title":"Fast Inverters over Finite Field Based on Euclid's Algorithm","volume":"72","author":"Araki K.","year":"1989","unstructured":"K. Araki , I. Fujita , and M. Morisue , \" Fast Inverters over Finite Field Based on Euclid's Algorithm ,\" Trans. of IEICE , vol. 72E , no. 11 , pp. 1230 -- 1234 , November 1989 . K. Araki, I. Fujita, and M. Morisue, \"Fast Inverters over Finite Field Based on Euclid's Algorithm,\" Trans. of IEICE, vol. 72E, no. 11, pp. 1230--1234, November 1989.","journal-title":"Trans. of IEICE"},{"key":"e_1_3_2_1_2_1","first-page":"272","volume-title":"IEE Proceedings on Computers and Digital Techniques","author":"Guo J.-H.","year":"1998","unstructured":"J.-H. Guo and C.-L. Wang , \"Hardware-efficient Systolic Architecture for Inversion and Division in GF(2m),\" in IEE Proceedings on Computers and Digital Techniques , 1998 , pp. 272 -- 278 . J.-H. Guo and C.-L. Wang, \"Hardware-efficient Systolic Architecture for Inversion and Division in GF(2m),\" in IEE Proceedings on Computers and Digital Techniques, 1998, pp. 272--278."},{"key":"e_1_3_2_1_3_1","volume-title":"VLSI Array Processors","author":"Kung S. Y.","year":"1988","unstructured":"S. Y. Kung , VLSI Array Processors , Prentice-Hall , Englewood Cliffs , New Jersy, 1988 . S. Y. Kung, VLSI Array Processors, Prentice-Hall, Englewood Cliffs, New Jersy, 1988."},{"key":"e_1_3_2_1_4_1","volume-title":"VLSI Digital Signal Processing Systems","author":"Parhi K. K.","year":"1999","unstructured":"K. K. Parhi , VLSI Digital Signal Processing Systems , John Wiley and Sons , New York , 1999 . K. K. Parhi, VLSI Digital Signal Processing Systems, John Wiley and Sons, New York, 1999."},{"key":"e_1_3_2_1_5_1","first-page":"5","article-title":"A VLSI Algorithm for Division in GF(2m) Based on Extended Binary GCD Algorithm","volume":"85","author":"Watanabe Y.","year":"2002","unstructured":"Y. Watanabe , N. Takagi , and K. Takagi , \" A VLSI Algorithm for Division in GF(2m) Based on Extended Binary GCD Algorithm ,\" IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences , vol. E85 -A, no. 5 , pp. 994--999, May 2002 . Y. Watanabe, N. Takagi, and K. Takagi, \"A VLSI Algorithm for Division in GF(2m) Based on Extended Binary GCD Algorithm,\" IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E85-A, no. 5, pp. 994--999, May 2002.","journal-title":"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences"},{"key":"e_1_3_2_1_6_1","first-page":"33","volume-title":"Low-Complexity Design,\" in Proceedings of ISCAS'01","author":"Wu C. H.","year":"2001","unstructured":"C. H. Wu , C. M. Wu , M. D. Shieh , and Y. T. Wang , \" Systolic VLSI Realization of a Novel Iterative Division Algorithm over GF(2m): a High-Speed , Low-Complexity Design,\" in Proceedings of ISCAS'01 , 2001 , pp. 33 -- 36 . C. H. Wu, C. M. Wu, M. D. Shieh, and Y. T. Wang, \"Systolic VLSI Realization of a Novel Iterative Division Algorithm over GF(2m): a High-Speed, Low-Complexity Design,\" in Proceedings of ISCAS'01, 2001, pp. 33--36."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_7_1","DOI":"10.1145\/988952.989064"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_8_1","DOI":"10.1016\/j.vlsi.2004.07.006"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_9_1","DOI":"10.1109\/TC.2003.1244950"}],"event":{"sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"],"acronym":"GLSVLSI05","name":"GLSVLSI05: Great Lakes Symposium on VLSI 2005","location":"Chicago Illinois USA"},"container-title":["Proceedings of the 15th ACM Great Lakes symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1057661.1057690","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1057661.1057690","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T21:25:59Z","timestamp":1750281959000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1057661.1057690"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005,4,17]]},"references-count":9,"alternative-id":["10.1145\/1057661.1057690","10.1145\/1057661"],"URL":"https:\/\/doi.org\/10.1145\/1057661.1057690","relation":{},"subject":[],"published":{"date-parts":[[2005,4,17]]},"assertion":[{"value":"2005-04-17","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}