{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:43:54Z","timestamp":1750308234305,"version":"3.41.0"},"reference-count":17,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2005,4,1]],"date-time":"2005-04-01T00:00:00Z","timestamp":1112313600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2005,4]]},"abstract":"<jats:p>Skewed logic circuits belong to a noise-tolerant high-performance static circuit family. Skewed logic circuits can achieve performance comparable to that of Domino logic circuits but with much lower power consumption. Two factors contribute to the reduction in power. First, by exploiting the static nature of skewed logic circuits, we can alleviate the cost of logic duplication which is typically required to overcome the logic reconvergence problem in both Domino logic and skewed logic circuits. Second, a selective clocking scheme can be applied to a skewed logic circuit to reduce the clock load and hence, clock power. In this article, we propose a two-step synthesis scheme of skewed logic circuits. In the first step, an integer linear programming-based approach is presented to overcome the logic reconvergence problem in skewed logic circuits with minimal logic duplication cost. In the second step, a dynamic programming-based heuristic is applied to achieve an optimal selective clocking scheme. Experimental results show that the average power saving of skewed logic circuits over Domino logic circuits is 41.1%.<\/jats:p>","DOI":"10.1145\/1059876.1059878","type":"journal-article","created":{"date-parts":[[2005,8,3]],"date-time":"2005-08-03T08:30:55Z","timestamp":1123057855000},"page":"205-228","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Synthesis of skewed logic circuits"],"prefix":"10.1145","volume":"10","author":[{"given":"Aiqun","family":"Cao","sequence":"first","affiliation":[{"name":"Synopsys, Inc., Mountain View, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Naran","family":"Sirisantana","sequence":"additional","affiliation":[{"name":"Intel Corporation, Hillsboro, OR"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Cheng-Kok","family":"Koh","sequence":"additional","affiliation":[{"name":"Purdue University, West Lafayette, IN"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kaushik","family":"Roy","sequence":"additional","affiliation":[{"name":"Purdue University, West Lafayette, IN"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2005,4]]},"reference":[{"volume-title":"Proceedings of the IEEE International Symposium on Quality Electronic Design","author":"Cao A.","key":"e_1_2_1_1_1","unstructured":"Cao , A. , Sirisantana , N. , Koh , C.-K. , and Roy , K . 2002. Synthesis of selectively clocked skewed logic circuits . In Proceedings of the IEEE International Symposium on Quality Electronic Design . San Jose, CA. 229--234. Cao, A., Sirisantana, N., Koh, C.-K., and Roy, K. 2002. Synthesis of selectively clocked skewed logic circuits. In Proceedings of the IEEE International Symposium on Quality Electronic Design. San Jose, CA. 229--234."},{"key":"e_1_2_1_2_1","volume-title":"Proceedings of the IEEE Asia South Pacific Design Automation Conference","author":"Cao A.","year":"1977","unstructured":"Cao , A. , Sirisantana , N. , Koh , C.-K. , and Roy , K . 2003. Integer linear programming-based synthesis of skewed logic circuits . In Proceedings of the IEEE Asia South Pacific Design Automation Conference . Kitakyushu, Japan. 820--823. 10.1145\/11 1977 2.1119953 Cao, A., Sirisantana, N., Koh, C.-K., and Roy, K. 2003. Integer linear programming-based synthesis of skewed logic circuits. In Proceedings of the IEEE Asia South Pacific Design Automation Conference. Kitakyushu, Japan. 820--823. 10.1145\/1119772.1119953"},{"volume-title":"Proceedings of the ACM\/IEEE Conference on Design Automation","author":"Dey S.","key":"e_1_2_1_3_1","unstructured":"Dey , S. , Brglez , F. , and Kedem , G . 1990. Corolla based circuit partitioning and resynthesis . In Proceedings of the ACM\/IEEE Conference on Design Automation . Orlando, FL. 607--612. 10.1145\/123186.123416 Dey, S., Brglez, F., and Kedem, G. 1990. Corolla based circuit partitioning and resynthesis. In Proceedings of the ACM\/IEEE Conference on Design Automation. Orlando, FL. 607--612. 10.1145\/123186.123416"},{"key":"e_1_2_1_4_1","doi-asserted-by":"crossref","first-page":"3","DOI":"10.1109\/JSSC.1983.1051937","article-title":"NORA: a race free dynamic CMOS technique for pipelined logic structures","volume":"18","author":"Goncalves N. F.","year":"1983","unstructured":"Goncalves , N. F. and Man , H. J. D. 1983 . NORA: a race free dynamic CMOS technique for pipelined logic structures . IEEE J. Solid State Circuits 18 , 3 (June), 261--266. Goncalves, N. F. and Man, H. J. D. 1983. NORA: a race free dynamic CMOS technique for pipelined logic structures. IEEE J. Solid State Circuits 18, 3 (June), 261--266.","journal-title":"IEEE J. Solid State Circuits"},{"volume-title":"Proceedings of the IEEE International Conference on Computer Design","author":"Kim C.","key":"e_1_2_1_5_1","unstructured":"Kim , C. , Lee , J. , Baek , K. H. , Martina , E. , and Kang , S. M . 2000. High-performance low-power skewed static logic in very deep-submicron (vdsm) technology . In Proceedings of the IEEE International Conference on Computer Design . Austin, TX. 59--64. Kim, C., Lee, J., Baek, K. H., Martina, E., and Kang, S. M. 2000. High-performance low-power skewed static logic in very deep-submicron (vdsm) technology. In Proceedings of the IEEE International Conference on Computer Design. Austin, TX. 59--64."},{"key":"e_1_2_1_6_1","doi-asserted-by":"crossref","first-page":"3","DOI":"10.1109\/JSSC.1982.1051786","article-title":"High-speed compact circuits with CMOS","volume":"17","author":"Krambeck R. H.","year":"1982","unstructured":"Krambeck , R. H. , Lee , C. M. , and Law , H.-F. S. 1982 . High-speed compact circuits with CMOS . IEEE J. Solid State Circuits 17 , 3 (June), 614--619. Krambeck, R. H., Lee, C. M., and Law, H.-F. S. 1982. High-speed compact circuits with CMOS. IEEE J. Solid State Circuits 17, 3 (June), 614--619.","journal-title":"IEEE J. Solid State Circuits"},{"volume-title":"Proceedings of the ACM\/IEEE International Workshop on Logic Synthesis","author":"Prasad M. R.","key":"e_1_2_1_7_1","unstructured":"Prasad , M. R. , Kirkpatrick , D. , Brayton , R. K. , and Sangiovanni-Vincentelli , A . 1997. Domino logic synthesis and technology mapping . In Proceedings of the ACM\/IEEE International Workshop on Logic Synthesis . Tahoe City, CA. Prasad, M. R., Kirkpatrick, D., Brayton, R. K., and Sangiovanni-Vincentelli, A. 1997. Domino logic synthesis and technology mapping. In Proceedings of the ACM\/IEEE International Workshop on Logic Synthesis. Tahoe City, CA."},{"volume-title":"Proceedings of the IEEE\/ACM International Conference on Computer Aided Design","author":"Puri R.","key":"e_1_2_1_8_1","unstructured":"Puri , R. , Bjorksten , A. , and Rosser , T. E . 1996. Logic optimization by output phase assignment in dynamic logic synthesis . In Proceedings of the IEEE\/ACM International Conference on Computer Aided Design . San Jose, CA. 2--8. Puri, R., Bjorksten, A., and Rosser, T. E. 1996. Logic optimization by output phase assignment in dynamic logic synthesis. In Proceedings of the IEEE\/ACM International Conference on Computer Aided Design. San Jose, CA. 2--8."},{"key":"e_1_2_1_9_1","doi-asserted-by":"crossref","first-page":"1016","DOI":"10.1109\/T-C.1973.223638","article-title":"Complete test sets for logic functions","volume":"11","author":"Reddy S. M.","year":"1973","unstructured":"Reddy , S. M. 1973 . Complete test sets for logic functions . IEEE Trans. Comput. C-22 , 11 ( Nov. ), 1016 -- 1020 . Reddy, S. M. 1973. Complete test sets for logic functions. IEEE Trans. Comput. C-22, 11 (Nov.), 1016--1020.","journal-title":"IEEE Trans. Comput. C-22"},{"key":"e_1_2_1_10_1","volume-title":"SIS: A system for sequential circuit synthesis. Tech. Rep. UCB\/ERL M92\/41","author":"Sentovich E. M.","year":"1992","unstructured":"Sentovich , E. M. , Singh , K. J. , Lavagno , L. , and 1992 . SIS: A system for sequential circuit synthesis. Tech. Rep. UCB\/ERL M92\/41 (May) University of California at Berkeley. Sentovich, E. M., Singh, K. J., Lavagno, L., and et al. 1992. SIS: A system for sequential circuit synthesis. Tech. Rep. UCB\/ERL M92\/41 (May) University of California at Berkeley."},{"volume-title":"Proceedings of the IEEE International Symposium on Low Power Electronics and Design","author":"Sirisantana N.","key":"e_1_2_1_11_1","unstructured":"Sirisantana , N. , Cao , A. , Davidson , S. , Koh , C.-K. , and Roy , K . 2001. Selectively clocked skewed logic (SCSL): A robust low-power logic style for high-performance applications . In Proceedings of the IEEE International Symposium on Low Power Electronics and Design . Huntington Beach, CA. 267--270. 10.1145\/383082.383160 Sirisantana, N., Cao, A., Davidson, S., Koh, C.-K., and Roy, K. 2001. Selectively clocked skewed logic (SCSL): A robust low-power logic style for high-performance applications. In Proceedings of the IEEE International Symposium on Low Power Electronics and Design. Huntington Beach, CA. 267--270. 10.1145\/383082.383160"},{"volume-title":"Proceedings of the IEEE International Conference on Computer Design","author":"Solomatnikov A.","key":"e_1_2_1_12_1","unstructured":"Solomatnikov , A. , Somasekhar , D. , Roy , K. , and Koh , C . -K. 2000. Skewed CMOS: Noise-immune high-performance low-power static circuit family . In Proceedings of the IEEE International Conference on Computer Design . Austin, TX. 241--246. Solomatnikov, A., Somasekhar, D., Roy, K., and Koh, C.-K. 2000. Skewed CMOS: Noise-immune high-performance low-power static circuit family. In Proceedings of the IEEE International Conference on Computer Design. Austin, TX. 241--246."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1016\/S0019-9958(83)80038-2"},{"volume-title":"Proceedings of the IEEE International Conference on Computer Design","author":"Thorp T.","key":"e_1_2_1_15_1","unstructured":"Thorp , T. , Yee , G. , and Sechen , C . 1999a. Design and synthesis of monotonic circuits . In Proceedings of the IEEE International Conference on Computer Design . Austin, TX. 569--572. Thorp, T., Yee, G., and Sechen, C. 1999a. Design and synthesis of monotonic circuits. In Proceedings of the IEEE International Conference on Computer Design. Austin, TX. 569--572."},{"volume-title":"Proceedings of the IEEE International Symposium on Low Power Electronics and Design","author":"Thorp T.","key":"e_1_2_1_16_1","unstructured":"Thorp , T. , Yee , G. , and Sechen , C . 1999b. Monotonic static CMOS and dual Vt technology . In Proceedings of the IEEE International Symposium on Low Power Electronics and Design . San Diego, CA. 151--155. 10.1145\/313817.313903 Thorp, T., Yee, G., and Sechen, C. 1999b. Monotonic static CMOS and dual Vt technology. In Proceedings of the IEEE International Symposium on Low Power Electronics and Design. San Diego, CA. 151--155. 10.1145\/313817.313903"},{"volume-title":"Proceedings of the IEEE\/ACM International Conference on Computer Aided Design","author":"Zhao M.","key":"e_1_2_1_17_1","unstructured":"Zhao , M. and Sapatnekar , S. S . 1998. Technology mapping for domino logic . In Proceedings of the IEEE\/ACM International Conference on Computer Aided Design . San Jose, CA. 248--251. 10.1145\/288548.288621 Zhao, M. and Sapatnekar, S. S. 1998. Technology mapping for domino logic. In Proceedings of the IEEE\/ACM International Conference on Computer Aided Design. San Jose, CA. 248--251. 10.1145\/288548.288621"},{"volume-title":"Proceedings of the IEEE International Symposium on Circuits and Systems","author":"Zhao M.","key":"e_1_2_1_18_1","unstructured":"Zhao , M. and Sapatnekar , S. S . 2000. Dual-monotonic domino gate mapping and optimal output phase assignment of domino logic . In Proceedings of the IEEE International Symposium on Circuits and Systems . Geneva, Switzerland. 309--312. Zhao, M. and Sapatnekar, S. S. 2000. Dual-monotonic domino gate mapping and optimal output phase assignment of domino logic. In Proceedings of the IEEE International Symposium on Circuits and Systems. Geneva, Switzerland. 309--312."}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1059876.1059878","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1059876.1059878","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T16:31:46Z","timestamp":1750264306000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1059876.1059878"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005,4]]},"references-count":17,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2005,4]]}},"alternative-id":["10.1145\/1059876.1059878"],"URL":"https:\/\/doi.org\/10.1145\/1059876.1059878","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"type":"print","value":"1084-4309"},{"type":"electronic","value":"1557-7309"}],"subject":[],"published":{"date-parts":[[2005,4]]},"assertion":[{"value":"2005-04-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}