{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:43:54Z","timestamp":1750308234496,"version":"3.41.0"},"reference-count":20,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2005,4,1]],"date-time":"2005-04-01T00:00:00Z","timestamp":1112313600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2005,4]]},"abstract":"<jats:p>\n            Scan-based transition tests are added to improve the detection of speed failures in sequential circuits. Empirical data suggests that both data volume and application time will increase dramatically for such transition testing. Techniques to address the above problem for a class of transition tests, called enhanced transition tests, are proposed in this article.The first technique, which combines the proposed transition test chains with the ATE repeat capability, reduces test data volume by 46.5% when compared with transition tests computed by a commercial transition test ATPG tool. However, the test application time may sometimes increase. To address the test time issue, a new DFT technique, Exchange Scan, is proposed. Exchange scan reduces both data volume and application time by 46.5%. These techniques rely on the use of hold-scan cells and highlight the effectiveness of hold-scan design to address test time and test data volume issues. In addition, we address the problem of yield loss due to incidental\n            <jats:italic>overtesting<\/jats:italic>\n            of functionally-untestable transition faults, and we formulate an efficient adjustment to the algorithm to keep the overtest ratio low. Our experimental results show that up to 14.5% reduction in overtest ratio can be achieved, with an average overtest reduction of 4.68%.\n          <\/jats:p>","DOI":"10.1145\/1059876.1059880","type":"journal-article","created":{"date-parts":[[2005,8,3]],"date-time":"2005-08-03T08:30:55Z","timestamp":1123057855000},"page":"258-278","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":11,"title":["Efficient techniques for transition testing"],"prefix":"10.1145","volume":"10","author":[{"given":"Xiao","family":"Liu","sequence":"first","affiliation":[{"name":"Virginia Tech"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael S.","family":"Hsiao","sequence":"additional","affiliation":[{"name":"Virginia Tech"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sreejit","family":"Chakravarty","sequence":"additional","affiliation":[{"name":"Intel Corporation"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Paul J.","family":"Thadikaran","sequence":"additional","affiliation":[{"name":"Intel Corporation"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2005,4]]},"reference":[{"volume-title":"Proceedings of the VLSI Testing Symposium. 42--47","author":"Chandra A.","key":"e_1_2_1_1_1","unstructured":"Chandra , A. and Chakrabarty , K . 2001. Frequency directed run length(FDR) codes with application to system on a chip data compression . In Proceedings of the VLSI Testing Symposium. 42--47 . Chandra, A. and Chakrabarty, K. 2001. Frequency directed run length(FDR) codes with application to system on a chip data compression. In Proceedings of the VLSI Testing Symposium. 42--47."},{"volume-title":"Proceedings of the IEEE International Test Conference. 365--374","author":"Dervisoglu B.","key":"e_1_2_1_2_1","unstructured":"Dervisoglu , B. and Stong , G . 1991. Design for testability: Using scanpath techniques for path-delay test and measurement . In Proceedings of the IEEE International Test Conference. 365--374 . Dervisoglu, B. and Stong, G. 1991. Design for testability: Using scanpath techniques for path-delay test and measurement. In Proceedings of the IEEE International Test Conference. 365--374."},{"volume-title":"Proceedings of the IEEE International Test Conference. 115--122","author":"Das D.","key":"e_1_2_1_3_1","unstructured":"Das , D. and Touba , N. A . 2000. Reducing Test Data Volume Using External\/BIST Hybrid Test Patterns . In Proceedings of the IEEE International Test Conference. 115--122 . Das, D. and Touba, N. A. 2000. Reducing Test Data Volume Using External\/BIST Hybrid Test Patterns. In Proceedings of the IEEE International Test Conference. 115--122."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/320954.320957"},{"volume-title":"Proceedings of the IEEE International Test Conference. 538--547","author":"Hsu F. F.","key":"e_1_2_1_5_1","unstructured":"Hsu , F. F. , Butler , K. M. , and Patel , J. H . 2001. A Case Study of the Illinois scan architecture . In Proceedings of the IEEE International Test Conference. 538--547 . Hsu, F. F., Butler, K. M., and Patel, J. H. 2001. A Case Study of the Illinois scan architecture. In Proceedings of the IEEE International Test Conference. 538--547."},{"volume-title":"29th International Symposium on Fault-Tolerant Computing. 260--267","author":"Hamzaoglu I.","key":"e_1_2_1_6_1","unstructured":"Hamzaoglu , I. and Patel , J. H . 1999. Reducing Test application time for full scan embedded cores . In 29th International Symposium on Fault-Tolerant Computing. 260--267 . Hamzaoglu, I. and Patel, J. H. 1999. Reducing Test application time for full scan embedded cores. In 29th International Symposium on Fault-Tolerant Computing. 260--267."},{"volume-title":"Proceedings of the VLSI Testing Symposium. 32--39","author":"Heragu K.","key":"e_1_2_1_7_1","unstructured":"Heragu , K. , Patel , J. H. , and Agrawal V. D . 1996. Segment delay faults: a new fault model . In Proceedings of the VLSI Testing Symposium. 32--39 . Heragu, K., Patel, J. H., and Agrawal V. D. 1996. Segment delay faults: a new fault model. In Proceedings of the VLSI Testing Symposium. 32--39."},{"key":"e_1_2_1_8_1","volume-title":"IEEE Design Automation and Test in Europe Conference. 949--953","author":"Hsiao M. S.","year":"2002","unstructured":"Hsiao , M. S. 2002 . Maximizing impossibilities for untestable fault identification . In IEEE Design Automation and Test in Europe Conference. 949--953 . Hsiao, M. S. 2002. Maximizing impossibilities for untestable fault identification. In IEEE Design Automation and Test in Europe Conference. 949--953."},{"volume-title":"Proceedings of the IEEE International Test Conference. 748--757","author":"Keller B.","key":"e_1_2_1_9_1","unstructured":"Keller , B. , Barnhart , C. , Brunkhorst , V. , Distler , F. , Ferko , A. , Farnsworth , O. , and Koeneman , B . 2001. OPMISR: The foundation of compressed ATPG vectors . In Proceedings of the IEEE International Test Conference. 748--757 . Keller, B., Barnhart, C., Brunkhorst, V., Distler, F., Ferko, A., Farnsworth, O., and Koeneman, B. 2001. OPMISR: The foundation of compressed ATPG vectors. In Proceedings of the IEEE International Test Conference. 748--757."},{"key":"e_1_2_1_10_1","volume-title":"IEEE European Test Conference. 237--242","author":"Koeneman B.","year":"1991","unstructured":"Koeneman , B. 1991 . LFSR-coded test patterns for scan designs . In IEEE European Test Conference. 237--242 . Koeneman, B. 1991. LFSR-coded test patterns for scan designs. In IEEE European Test Conference. 237--242."},{"volume-title":"IEEE\/ACM International Conference on Computer-Aided Design. 74--78","author":"Lee K.-J.","key":"e_1_2_1_11_1","unstructured":"Lee , K.-J. , Chen , J.,-J. , and Huang , C . -H. 1998. Using a single input to support multiple scan chains . In IEEE\/ACM International Conference on Computer-Aided Design. 74--78 . 10.1145\/288548.288563 Lee, K.-J., Chen, J.,-J., and Huang, C.-H. 1998. Using a single input to support multiple scan chains. In IEEE\/ACM International Conference on Computer-Aided Design. 74--78. 10.1145\/288548.288563"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1024696110831"},{"volume-title":"Proceedings of the VLSI Testing Symposium. 15--20","author":"Lai W. C.","key":"e_1_2_1_13_1","unstructured":"Lai , W. C. , Kristic , A. , and Cheng , K. T . 2000a. On testing the path delay faults of a microprocessor using its instrcution set . In Proceedings of the VLSI Testing Symposium. 15--20 . Lai, W. C., Kristic, A., and Cheng, K. T. 2000a. On testing the path delay faults of a microprocessor using its instrcution set. In Proceedings of the VLSI Testing Symposium. 15--20."},{"volume-title":"Proceedings of the IEEE International Test Conference. 1080--1089","author":"Lai W. C.","key":"e_1_2_1_14_1","unstructured":"Lai , W. C. , Kristic , A. , and Cheng , K. T . 2000b. Test program synthesis for path delay faults in microprocessor cores . In Proceedings of the IEEE International Test Conference. 1080--1089 . Lai, W. C., Kristic, A., and Cheng, K. T. 2000b. Test program synthesis for path delay faults in microprocessor cores. In Proceedings of the IEEE International Test Conference. 1080--1089."},{"key":"e_1_2_1_15_1","volume-title":"Proceedings of the IEEE International Test Conference. 624--633","author":"Rearick J.","year":"2001","unstructured":"Rearick , J. 2001 . Too much delay fault coverage is a bad thing . In Proceedings of the IEEE International Test Conference. 624--633 . Rearick, J. 2001. Too much delay fault coverage is a bad thing. In Proceedings of the IEEE International Test Conference. 624--633."},{"key":"e_1_2_1_16_1","volume-title":"Proceedings of the IEEE International Test Conference. 342--349","author":"Smith G. L.","year":"1985","unstructured":"Smith , G. L. 1985 . Model for delay faults based upon paths . In Proceedings of the IEEE International Test Conference. 342--349 . Smith, G. L. 1985. Model for delay faults based upon paths. In Proceedings of the IEEE International Test Conference. 342--349."},{"key":"e_1_2_1_17_1","first-page":"8","article-title":"Scan-based transition test","volume":"12","author":"Savir J.","year":"1993","unstructured":"Savir , J. and Patil , S. 1993 . Scan-based transition test . IEEE Trans. on Comput.-Aid. Des. Integr. Circuit Syst. 12 , 8 (Aug.). Savir, J. and Patil, S. 1993. Scan-based transition test. IEEE Trans. on Comput.-Aid. Des. Integr. Circuit Syst. 12, 8 (Aug.).","journal-title":"IEEE Trans. on Comput.-Aid. Des. Integr. Circuit Syst."},{"volume-title":"Proceedings of the VLSI Testing Symposium. 284--290","author":"Savir J.","key":"e_1_2_1_18_1","unstructured":"Savir , J. and Patil , S . 1994. On broad-side delay test . In Proceedings of the VLSI Testing Symposium. 284--290 . Savir, J. and Patil, S. 1994. On broad-side delay test. In Proceedings of the VLSI Testing Symposium. 284--290."},{"volume-title":"Proceedings of the VLSI Testing Symposium. 3--8.","author":"Tendulkar N.","key":"e_1_2_1_19_1","unstructured":"Tendulkar , N. , Raina , R. , Woltenburg , R. , Lin , X. , Swanson , B. , and Aldrich , G . 2002. Novel techniques for achieving high at-speed transition fault coverage for Motorola's microprocessors based on PowerPC instruction set architecture . In Proceedings of the VLSI Testing Symposium. 3--8. Tendulkar, N., Raina, R., Woltenburg, R., Lin, X., Swanson, B., and Aldrich, G. 2002. Novel techniques for achieving high at-speed transition fault coverage for Motorola's microprocessors based on PowerPC instruction set architecture. In Proceedings of the VLSI Testing Symposium. 3--8."},{"key":"e_1_2_1_20_1","doi-asserted-by":"crossref","unstructured":"Waicukauski J. A. Lindbloom E. Rosen B. K. and Iyengar V. S. 1987. Transition fault simulation. IEEE Des. Test Comput. (April) 32--38.  Waicukauski J. A. Lindbloom E. Rosen B. K. and Iyengar V. S. 1987. Transition fault simulation. IEEE Des. Test Comput. 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