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This article describes a detailed and flexible power model which has been integrated in the widely used Versatile Place and Route (VPR) CAD tool. This power model estimates the dynamic, short-circuit, and leakage power consumed by FPGAs. It is the first flexible power model developed to evaluate architectural tradeoffs and the efficiency of power-aware CAD tools for a variety of FPGA architectures, and is freely available for noncommercial use. The model is flexible, in that it can estimate the power for a wide variety of FPGA architectures, and it is fast, in that it does not require extensive simulation, meaning it can be used to explore a large architectural space. We show how the model can be used to investigate the impact of various architectural parameters on the energy consumed by the FPGA, focusing on the segment length, switch block topology, lookuptable size, and cluster size.<\/jats:p>","DOI":"10.1145\/1059876.1059881","type":"journal-article","created":{"date-parts":[[2005,8,3]],"date-time":"2005-08-03T08:30:55Z","timestamp":1123057855000},"page":"279-302","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":136,"title":["A detailed power model for field-programmable gate arrays"],"prefix":"10.1145","volume":"10","author":[{"given":"Kara K. W.","family":"Poon","sequence":"first","affiliation":[{"name":"University of British Columbia, BC, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Steven J. 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Kang S. M. and Leblebici Y. 1999. CMOS Digital Integrated Circuits: Analysis and Design. McGraw-Hill New York NY."},{"key":"e_1_2_1_11_1","volume-title":"Proceedings of the 15th International Conference on VLSI Design (Jan.).","author":"Kumar R.","unstructured":"Kumar , R. and Ravikumar , C. P . 2002. Leakage power estimation for deep submicron circuits in an ASIC design environment . In Proceedings of the 15th International Conference on VLSI Design (Jan.). Kumar, R. and Ravikumar, C. P. 2002. Leakage power estimation for deep submicron circuits in an ASIC design environment. In Proceedings of the 15th International Conference on VLSI Design (Jan.)."},{"key":"e_1_2_1_12_1","volume-title":"Proceedings of the IEEE International Conference on Computer-Aided Design. 10","author":"Lamoureux J.","year":"2003","unstructured":"Lamoureux , J. and Wilton , S . 2003. On the interaction between power-aware FPGA CAD algorithms . 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In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design. Najm, F. N. 1995b. Power estimation techniques for integrated circuits. In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design."},{"key":"e_1_2_1_21_1","volume-title":"Proceedings of the ACM\/IEEE Design Automation Conference. 612--617","author":"Najm F. N.","year":"1995","unstructured":"Najm , F. N. 1995 a. Feedback, correlation, and delay concerns in the power estimation of VLSI circuits . In Proceedings of the ACM\/IEEE Design Automation Conference. 612--617 . 10.1145\/217474.217598 Najm, F. N. 1995a. Feedback, correlation, and delay concerns in the power estimation of VLSI circuits. In Proceedings of the ACM\/IEEE Design Automation Conference. 612--617. 10.1145\/217474.217598"},{"key":"e_1_2_1_22_1","volume-title":"Digital Integrated Circuits: A Design Perspective","author":"Rabaey J. M.","unstructured":"Rabaey , J. M. 1996. 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In Proceedings of the ACM International Symposium on Field-Programmable Gate Array. 157--164 . 10.1145\/503048.503072 Shang, L., Kaviani, A. S., and Bathala, K. 2002. Dynamic power consumption in virtex-II FPGA family. In Proceedings of the ACM International Symposium on Field-Programmable Gate Array. 157--164. 10.1145\/503048.503072"},{"key":"e_1_2_1_25_1","doi-asserted-by":"crossref","unstructured":"Toh K. Y. Ko P. K. and Meyer R. G. 1988. An engineering model for short-channel MOS devices. IEEE J. Solid-State Circ. SC-23 4 (Aug.) 950--958.  Toh K. Y. Ko P. K. and Meyer R. G. 1988. An engineering model for short-channel MOS devices. IEEE J. Solid-State Circ. SC-23 4 (Aug.) 950--958.","DOI":"10.1109\/4.346"},{"key":"e_1_2_1_26_1","volume-title":"Proceedings of the Design Automation Conference. 18--23","author":"Tsui C. Y.","year":"1962","unstructured":"Tsui , C. Y. , Pedram , M. , and Despain , A. M . 1994. Exact and approximate methods for calculating signal and transition probabilities in FSMs . In Proceedings of the Design Automation Conference. 18--23 . 10.1145\/ 1962 44.196255 Tsui, C. Y., Pedram, M., and Despain, A. M. 1994. Exact and approximate methods for calculating signal and transition probabilities in FSMs. In Proceedings of the Design Automation Conference. 18--23. 10.1145\/196244.196255"},{"key":"e_1_2_1_27_1","volume-title":"Proceedings of the 2001 IEEE International Conference on Acoustics, Speech, and Signal Processing","volume":"2","author":"Tuan T.","year":"2001","unstructured":"Tuan , T. , Li , S.-F. , and Rabaey , J . 2001. Reconfigurable platform design for wireless protocol processors . In Proceedings of the 2001 IEEE International Conference on Acoustics, Speech, and Signal Processing , vol. 2 ( May ). 893--896. 10.1109\/ICASSP. 2001 .941059 Tuan, T., Li, S.-F., and Rabaey, J. 2001. Reconfigurable platform design for wireless protocol processors. In Proceedings of the 2001 IEEE International Conference on Acoustics, Speech, and Signal Processing, vol. 2 (May). 893--896. 10.1109\/ICASSP.2001.941059"},{"key":"e_1_2_1_28_1","volume-title":"Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low Power Design (Volta99)","author":"Wang Q.","unstructured":"Wang , Q. and Vrudhula , S. B. K. 1999. A new short circuit power model for complex CMOS gates . In Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low Power Design (Volta99) . 98--106. Wang, Q. and Vrudhula, S. B. K. 1999. A new short circuit power model for complex CMOS gates. In Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low Power Design (Volta99). 98--106."},{"key":"e_1_2_1_29_1","volume-title":"Understanding XC9500XL CPLD power, ver. 1.1. Xilinx","author":"Xilinx","unstructured":"Xilinx . 1999. Understanding XC9500XL CPLD power, ver. 1.1. Xilinx , Inc., San Jose, CA. Web site: www.xilinx.com. Xilinx. 1999. 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