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In the presence of unpredictabilities, meeting the clock latency constraint cannot be guaranteed. This article proposes a novel risk management based technique to solve this problem. Here, the risk management paradigm assigns a quantified value to the amount of risk the designer is willing to take on the clock cycle constraint. The algorithm then assigns voltages in order to meet the expected value of clock cycle constraint while keeping the maximum delay within the specified \u201crisk\u201d and minimizing the power. The proposed algorithm is based on dynamic programming and is optimal for trees. Experimental results show that the traditional voltage scheduling approach is incapable of handling unpredictabilities. Our approach is capable of generating an effective tradeoff between power and \u201crisk\u201d: the more the risk, the less the power. The results show that a small increase in design risk positively affects the power dissipation.<\/jats:p>","DOI":"10.1145\/1059876.1059884","type":"journal-article","created":{"date-parts":[[2005,8,3]],"date-time":"2005-08-03T08:30:55Z","timestamp":1123057855000},"page":"354-368","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Voltage scheduling under unpredictabilities: a risk management paradigm"],"prefix":"10.1145","volume":"10","author":[{"given":"Azadeh","family":"Davoodi","sequence":"first","affiliation":[{"name":"University of Maryland, College Park, MD"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ankur","family":"Srivastava","sequence":"additional","affiliation":[{"name":"University of Maryland, College Park, MD"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2005,4]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"crossref","first-page":"4","DOI":"10.1109\/4.126534","article-title":"Low power CMOS digital design","volume":"27","author":"Chandrakasan A. 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In Proceedings of the International Symposium on Microarchitecture."},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/225871.225877"},{"volume-title":"Proceedings of the International Workshop on Low Power Design. 10","author":"Raje S.","key":"e_1_2_1_11_1","unstructured":"Raje , S. and Sarrafzadeh , M . 1995. Variable voltage scheduling . In Proceedings of the International Workshop on Low Power Design. 10 .1145\/224081.224084 Raje, S. and Sarrafzadeh, M. 1995. Variable voltage scheduling. In Proceedings of the International Workshop on Low Power Design. 10.1145\/224081.224084"},{"volume-title":"Proceedings of the International Conference on Computer Aided Design. 10","author":"Srivastava A.","key":"e_1_2_1_12_1","unstructured":"Srivastava , A. and Sarrafzadeh , M . 2002. Predictability: Definition, analysis and optimization . In Proceedings of the International Conference on Computer Aided Design. 10 .1145\/774572.774589 Srivastava, A. and Sarrafzadeh, M. 2002. Predictability: Definition, analysis and optimization. In Proceedings of the International Conference on Computer Aided Design. 10.1145\/774572.774589"},{"volume-title":"Proceedings of the IEEE International Conference on Computer Aided Design. 62--65","author":"Tellez G. E.","key":"e_1_2_1_13_1","unstructured":"Tellez , G. E. , Farrahi , A. , and Sarrafzadeh , M . 1995. Activity-driven clock design for low power circuits . In Proceedings of the IEEE International Conference on Computer Aided Design. 62--65 . Tellez, G. E., Farrahi, A., and Sarrafzadeh, M. 1995. Activity-driven clock design for low power circuits. In Proceedings of the IEEE International Conference on Computer Aided Design. 62--65."},{"volume-title":"Proceedings of the International Symposium on System Synthesis. 66--71","author":"Tomiyama H.","key":"e_1_2_1_14_1","unstructured":"Tomiyama , H. , Inoue , A. , and Yasuura , H . 1998. Statistical performance driven module binding in high level synthesis . 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