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Dynamic power has been the most significant factor, but leakage will become increasingly significant in future. It is predicted that leakage will shortly be the most significant cost as it grows at about a 5\u00d7 rate per generation. Thus, reducing leakage is essential for future processor design. Since large caches occupy most of the area, they are one of the leakiest structures in the chip and hence, a main source of energy consumption for future processors.This paper introduces\n            <jats:italic>IATAC<\/jats:italic>\n            (inter-access time per access count), a new hardware technique to reduce cache leakage for L2 caches.\n            <jats:italic>IATAC<\/jats:italic>\n            dynamically adapts the cache size to the program requirements turning off cache lines whose content is not likely to be reused. Our evaluation shows that this approach outperforms all previous state-of-the-art techniques.\n            <jats:italic>IATAC<\/jats:italic>\n            turns off 65% of the cache lines across different L2 cache configurations with a very small performance degradation of around 2%.\n          <\/jats:p>","DOI":"10.1145\/1061267.1061271","type":"journal-article","created":{"date-parts":[[2005,8,1]],"date-time":"2005-08-01T17:31:42Z","timestamp":1122917502000},"page":"55-77","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":76,"title":["IATAC: a smart predictor to turn-off L2 cache lines"],"prefix":"10.1145","volume":"2","author":[{"given":"Jaume","family":"Abella","sequence":"first","affiliation":[{"name":"Universitat Polit\u00e8cnica de Catalunya-Barcelona, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Antonio","family":"Gonz\u00e1lez","sequence":"additional","affiliation":[{"name":"Intel Barcelona Research Center, Intel Labs-UPC, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xavier","family":"Vera","sequence":"additional","affiliation":[{"name":"Intel Barcelona Research Center, Intel Labs-UPC, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael F. 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