{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,27]],"date-time":"2026-02-27T03:45:17Z","timestamp":1772163917908,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":26,"publisher":"ACM","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2005,6,15]]},"DOI":"10.1145\/1065910.1065929","type":"proceedings-article","created":{"date-parts":[[2005,8,3]],"date-time":"2005-08-03T04:31:47Z","timestamp":1123043507000},"page":"127-136","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":13,"title":["Static strands"],"prefix":"10.1145","author":[{"given":"Peter G.","family":"Sassone","sequence":"first","affiliation":[{"name":"Georgia Institute of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D. Scott","family":"Wills","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gabriel H.","family":"Loh","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2005,6,15]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"Q1","article-title":"Efficient exploitation of parallelism on Pentium III and Pentium 4 processor-based systems","author":"Bik A.","year":"2001","unstructured":"A. Bik , M. Girkar , P. Grey , and X. Tian . Efficient exploitation of parallelism on Pentium III and Pentium 4 processor-based systems . In Intel Technology Journal , Q1 2001 . A. Bik, M. Girkar, P. Grey, and X. Tian. Efficient exploitation of parallelism on Pentium III and Pentium 4 processor-based systems. In Intel Technology Journal, Q1 2001.","journal-title":"Intel Technology Journal"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.15"},{"key":"e_1_3_2_1_3_1","volume-title":"ARM","author":"Brash D.","year":"2002","unstructured":"D. Brash . The ARM architecture version 6 (ARMv6). White paper , ARM , 2002 . D. Brash. The ARM architecture version 6 (ARMv6). White paper, ARM, 2002."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.5555\/774861.774864"},{"key":"e_1_3_2_1_6_1","volume-title":"Proceedings of IEEE Custom Integrated Circuits Conference","author":"Cao Y.","year":"2000","unstructured":"Y. Cao , T. Sato , D. Sylvester , M. Orshansky , and C. Hu . New paradigm of predictive mosfet and interconnect modeling for early circuit design . In Proceedings of IEEE Custom Integrated Circuits Conference , June 2000 . Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu. New paradigm of predictive mosfet and interconnect modeling for early circuit design. In Proceedings of IEEE Custom Integrated Circuits Conference, June 2000."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.5"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/320080.320093"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.5555\/545215.545221"},{"issue":"2","key":"e_1_3_2_1_10_1","article-title":"The Intel Pentium M processor: Microarchitecture and performance","volume":"7","author":"Gochman S.","year":"2003","unstructured":"S. Gochman , R. Ronen , I. Anati , A. Berkovits , T. Kurts , A. Naveh , A. Saeed , Z. Sperber , and R. Valentine . The Intel Pentium M processor: Microarchitecture and performance . Intel Technology Journal , 7 ( 2 ), May 2003 . S. Gochman, R. Ronen, I. Anati, A. Berkovits, T. Kurts, A. Naveh, A. Saeed, Z. Sperber, and R. Valentine. The Intel Pentium M processor: Microarchitecture and performance. Intel Technology Journal, 7(2), May 2003.","journal-title":"Intel Technology Journal"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF01205185"},{"key":"e_1_3_2_1_12_1","unstructured":"IBM Corporation. PowerPC 750 RISC Microprocessor Technical Summary. www.ibm.com.  IBM Corporation. PowerPC 750 RISC Microprocessor Technical Summary. www.ibm.com."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1225977"},{"key":"e_1_3_2_1_14_1","volume-title":"Proceedings of the International Symposium on Computer Architecture","author":"Kim H.","year":"2002","unstructured":"H. Kim and J. Smith . Instruction-level distributed processing . In Proceedings of the International Symposium on Computer Architecture , May 2002 . H. Kim and J. Smith. Instruction-level distributed processing. In Proceedings of the International Symposium on Computer Architecture, May 2002."},{"key":"e_1_3_2_1_15_1","volume-title":"Proceedings of the International Conference on Code Generation and Optimization","author":"Kim H.","year":"2003","unstructured":"H. Kim and J. Smith . Dynamic binary translation for accumulator-oriented architectures . In Proceedings of the International Conference on Code Generation and Optimization , Mar. 2003 . H. Kim and J. Smith. Dynamic binary translation for accumulator-oriented architectures. In Proceedings of the International Conference on Code Generation and Optimization, Mar. 2003."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859623"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.5555\/956417.956563"},{"key":"e_1_3_2_1_18_1","volume-title":"Proceedings of the International Symposium on Microarchitecture","author":"Lee C.","year":"1997","unstructured":"C. Lee , M. Potkonjak , and W. Mangione-Smith . Mediabench: A tool for evaluating multimedia and communications systems . In Proceedings of the International Symposium on Microarchitecture , Dec. 1997 . C. Lee, M. Potkonjak, and W. Mangione-Smith. Mediabench: A tool for evaluating multimedia and communications systems. In Proceedings of the International Symposium on Microarchitecture, Dec. 1997."},{"key":"e_1_3_2_1_20_1","volume-title":"A superstrand architecture. Technical Memo 14","author":"Marquez A.","year":"1997","unstructured":"A. Marquez , K. Theobald , X. Tang , and G. Gao . A superstrand architecture. Technical Memo 14 , University of Delaware , Computer Architecture and Parallel Systems Laboratory, 1997 . A. Marquez, K. Theobald, X. Tang, and G. Gao. A superstrand architecture. Technical Memo 14, University of Delaware, Computer Architecture and Parallel Systems Laboratory, 1997."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2005.16"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/264107.264201"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.5555\/774861.774880"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.5555\/545215.545251"},{"key":"e_1_3_2_1_25_1","unstructured":"Renesas Technology. SH-4A Software Manual. www.renesas.com.  Renesas Technology. SH-4A Software Manual. www.renesas.com."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.16"},{"key":"e_1_3_2_1_27_1","unstructured":"UC Berkeley. Berkeley predictive technology model. www-device.eecs.berkeley.edu\/~ptm.  UC Berkeley. Berkeley predictive technology model. www-device.eecs.berkeley.edu\/~ptm."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.5555\/998680.1006721"}],"event":{"name":"LCTES05: Languages, Compilers, and Tools for Embedded Systems 2005","location":"Chicago Illinois USA","acronym":"LCTES05","sponsor":["SIGPLAN ACM Special Interest Group on Programming Languages","ACM Association for Computing Machinery","SIGBED ACM Special Interest Group on Embedded Systems"]},"container-title":["Proceedings of the 2005 ACM SIGPLAN\/SIGBED conference on Languages, compilers, and tools for embedded systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1065910.1065929","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,9,4]],"date-time":"2023-09-04T08:41:01Z","timestamp":1693816861000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1065910.1065929"}},"subtitle":["safely collapsing dependence chains for increasing embedded power efficiency"],"short-title":[],"issued":{"date-parts":[[2005,6,15]]},"references-count":26,"alternative-id":["10.1145\/1065910.1065929","10.1145\/1065910"],"URL":"https:\/\/doi.org\/10.1145\/1065910.1065929","relation":{"is-identical-to":[{"id-type":"doi","id":"10.1145\/1070891.1065929","asserted-by":"object"}]},"subject":[],"published":{"date-parts":[[2005,6,15]]},"assertion":[{"value":"2005-06-15","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}