{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,27]],"date-time":"2026-02-27T03:45:54Z","timestamp":1772163954512,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":43,"publisher":"ACM","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2005,6,15]]},"DOI":"10.1145\/1065910.1065930","type":"proceedings-article","created":{"date-parts":[[2005,8,3]],"date-time":"2005-08-03T04:31:47Z","timestamp":1123043507000},"page":"137-146","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["Complementing software pipelining with software thread integration"],"prefix":"10.1145","author":[{"given":"Won","family":"So","sequence":"first","affiliation":[{"name":"North Carolina State University, Raleigh, NC"}]},{"given":"Alexander G.","family":"Dean","sequence":"additional","affiliation":[{"name":"North Carolina State University, Raleigh, NC"}]}],"member":"320","published-online":{"date-parts":[[2005,6,15]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.5555\/645387.651543"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/567067.567085"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1016\/0167-6423(92)90005-V"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1016\/0743-7315(88)90002-0"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.5555\/795698.798430"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.5555\/266800.266835"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1016\/0096-0551(93)90005-L"},{"key":"e_1_3_2_1_8_1","first-page":"103","volume-title":"Proceedings of the 23rd IEEE Real-Time Systems Symposium (RTSS'02)","author":"Dean A. G.","unstructured":"A. G. Dean . Compiling for fine-grain concurrency: Planning and performing software thread integration . In Proceedings of the 23rd IEEE Real-Time Systems Symposium (RTSS'02) , page 103 . IEEE Computer Society, 2002. A. G. Dean. Compiling for fine-grain concurrency: Planning and performing software thread integration. In Proceedings of the 23rd IEEE Real-Time Systems Symposium (RTSS'02), page 103. IEEE Computer Society, 2002."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.5555\/827270.829058"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.5555\/827271.829092"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/207110.207119"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/24039.24041"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/36583.36598"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605428"},{"key":"e_1_3_2_1_15_1","volume-title":"Proceedings of the 3rd Workshop on Media and Stream Processors","author":"Granston E.","year":"2001","unstructured":"E. Granston , R. Scales , E. Stotzer , A. Ward , and J. Zbiciak . Controlling code size of software-pipelined loops on the TMS320C6000 VLIW DSP architecture . In Proceedings of the 3rd Workshop on Media and Stream Processors , Dec. 2001 . E. Granston, R. Scales, E. Stotzer, A. Ward, and J. Zbiciak. Controlling code size of software-pipelined loops on the TMS320C6000 VLIW DSP architecture. In Proceedings of the 3rd Workshop on Media and Stream Processors, Dec. 2001."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.97300"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.5555\/645671.665383"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.5555\/645673.758039"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/155090.155115"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.918001"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/53990.54022"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.5555\/243846.243879"},{"key":"e_1_3_2_1_23_1","volume-title":"Proceedings of the 6th Workshop on Media and Streaming Processors","author":"Narayanan M.","year":"2004","unstructured":"M. Narayanan and K. A. Yelick . Generating permutation instructions from a high-level description . In Proceedings of the 6th Workshop on Media and Streaming Processors , 2004 . M. Narayanan and K. A. Yelick. Generating permutation instructions from a high-level description. In Proceedings of the 6th Workshop on Media and Streaming Processors, 2004."},{"key":"e_1_3_2_1_24_1","volume-title":"Trimaran - an infrastructure for compiler research in instruction-level parallelism - user manual","author":"Nene A.","year":"1998","unstructured":"A. Nene , S. Talla , B. Goldberg , and R. Rabbah . Trimaran - an infrastructure for compiler research in instruction-level parallelism - user manual . New York University , 1998 . A. Nene, S. Talla, B. Goldberg, and R. Rabbah. Trimaran - an infrastructure for compiler research in instruction-level parallelism - user manual. New York University, 1998."},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.5555\/789083.1022764"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/513829.513850"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.5555\/645989.674315"},{"key":"e_1_3_2_1_28_1","first-page":"27","volume-title":"Proceedings of Seventh Workshop on Interaction between Compilers and Computer Architecture (INTERACT-7)","author":"So W.","year":"2003","unstructured":"W. So and A. G. Dean . Procedure cloning and integration for converting parallelism from coarse to fine grain . In Proceedings of Seventh Workshop on Interaction between Compilers and Computer Architecture (INTERACT-7) , pages 27 -- 36 . IEEE Computer Society , Feb. 2003 . W. So and A. G. Dean. Procedure cloning and integration for converting parallelism from coarse to fine grain. In Proceedings of Seventh Workshop on Interaction between Compilers and Computer Architecture (INTERACT-7), pages 27--36. IEEE Computer Society, Feb. 2003."},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1007\/s002360050095"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.5555\/243846.243893"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/314403.314427"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/255305.255322"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.997877"},{"key":"e_1_3_2_1_34_1","volume-title":"Mar.","author":"Instruments Texas","year":"2000","unstructured":"Texas Instruments . Code Composer Studio User's Guide (Rev. B) , Mar. 2000 . Texas Instruments. Code Composer Studio User's Guide (Rev. B), Mar. 2000."},{"key":"e_1_3_2_1_35_1","volume-title":"Sept.","author":"Instruments Texas","year":"2000","unstructured":"Texas Instruments . TMS320C6000 CPU and Instruction Set Reference Guide , Sept. 2000 . Texas Instruments. TMS320C6000 CPU and Instruction Set Reference Guide, Sept. 2000."},{"key":"e_1_3_2_1_36_1","volume-title":"Jan.","author":"Instruments Texas","year":"2001","unstructured":"Texas Instruments . TMS320C64x Technical Overview , Jan. 2001 . Texas Instruments. TMS320C64x Technical Overview, Jan. 2001."},{"key":"e_1_3_2_1_37_1","volume-title":"Apr.","author":"Instruments Texas","year":"2002","unstructured":"Texas Instruments . TMS320C64x DSP Library Programmer's Reference , Apr. 2002 . Texas Instruments. TMS320C64x DSP Library Programmer's Reference, Apr. 2002."},{"key":"e_1_3_2_1_38_1","volume-title":"Apr.","author":"Instruments Texas","year":"2002","unstructured":"Texas Instruments . TMS320C64x Image\/Video Processing Library Programmer's Reference , Apr. 2002 . Texas Instruments. TMS320C64x Image\/Video Processing Library Programmer's Reference, Apr. 2002."},{"key":"e_1_3_2_1_39_1","volume-title":"Sept.","author":"Instruments Texas","year":"2004","unstructured":"Texas Instruments . TMS320C6000 DSP Peripherals Overview Reference Guide (Rev. G) , Sept. 2004 . Texas Instruments. TMS320C6000 DSP Peripherals Overview Reference Guide (Rev. G), Sept. 2004."},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.5555\/647478.727935"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.5555\/144953.145796"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/155090.155118"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.5555\/225160.225180"}],"event":{"name":"LCTES05: Languages, Compilers, and Tools for Embedded Systems 2005","location":"Chicago Illinois USA","acronym":"LCTES05","sponsor":["SIGPLAN ACM Special Interest Group on Programming Languages","ACM Association for Computing Machinery","SIGBED ACM Special Interest Group on Embedded Systems"]},"container-title":["Proceedings of the 2005 ACM SIGPLAN\/SIGBED conference on Languages, compilers, and tools for embedded systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1065910.1065930","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,9,4]],"date-time":"2023-09-04T08:41:04Z","timestamp":1693816864000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1065910.1065930"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005,6,15]]},"references-count":43,"alternative-id":["10.1145\/1065910.1065930","10.1145\/1065910"],"URL":"https:\/\/doi.org\/10.1145\/1065910.1065930","relation":{"is-identical-to":[{"id-type":"doi","id":"10.1145\/1070891.1065930","asserted-by":"object"}]},"subject":[],"published":{"date-parts":[[2005,6,15]]},"assertion":[{"value":"2005-06-15","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}