{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:41:40Z","timestamp":1750308100002,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":11,"publisher":"ACM","license":[{"start":{"date-parts":[[2005,6,25]],"date-time":"2005-06-25T00:00:00Z","timestamp":1119657600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2005,6,25]]},"DOI":"10.1145\/1068009.1068238","type":"proceedings-article","created":{"date-parts":[[2005,8,3]],"date-time":"2005-08-03T08:31:47Z","timestamp":1123057907000},"page":"1441-1445","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Multi-level genetic algorithm (MLGA) for the construction of clock binary tree"],"prefix":"10.1145","author":[{"given":"Nan","family":"Guofang","sequence":"first","affiliation":[{"name":"Tianjin University, Tianjin, P.R. China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Li","family":"Minqiang","sequence":"additional","affiliation":[{"name":"Tianjin University, Tianjin, P.R. China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kou","family":"Jisong","sequence":"additional","affiliation":[{"name":"Tianjin University, Tianjin, P.R. China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2005,6,25]]},"reference":[{"volume-title":"Algorithms for VLSI Physical Design Automation","author":"Naveed A.","key":"e_1_3_2_1_1_1","unstructured":"Naveed A. Sherwani , Algorithms for VLSI Physical Design Automation , Kluwer Academic Publishers , ISBN 0-7923-9294-9. Naveed A.Sherwani, Algorithms for VLSI Physical Design Automation, Kluwer Academic Publishers, ISBN 0-7923-9294-9."},{"issue":"11","key":"e_1_3_2_1_2_1","first-page":"799","article-title":"Zero skew clock routing with minimum wirelength, Circuits and Systems II: Analog and Digital Signal Processing","volume":"39","author":"Ting-Hai Chao","year":"1992","unstructured":"Ting-Hai Chao , Yu-Chin Hsu, Jan-Ming Ho , Kahng A B , Zero skew clock routing with minimum wirelength, Circuits and Systems II: Analog and Digital Signal Processing , IEEE Transactions on , 1992 , 39 ( 11 ): 799 -- 814 Ting-Hai Chao, Yu-Chin Hsu, Jan-Ming Ho, Kahng A B, Zero skew clock routing with minimum wirelength, Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, 1992, 39(11): 799--814","journal-title":"IEEE Transactions on"},{"key":"e_1_3_2_1_3_1","first-page":"66","article-title":"Bounded-skew clock and Steiner routing under Elmore delay, Computer-Aided Design, 1995","volume":"1995","author":"Cong J","unstructured":"Cong J , Kahng A B , Koh C K , Tsao C W , Bounded-skew clock and Steiner routing under Elmore delay, Computer-Aided Design, 1995 . ICCAD-95 . 1995 : 66 -- 71 Cong J, Kahng A B, Koh C K, Tsao C W, Bounded-skew clock and Steiner routing under Elmore delay, Computer-Aided Design, 1995. ICCAD-95.1995: 66--71","journal-title":"ICCAD-95"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/123186.123406"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/127601.127688"},{"key":"e_1_3_2_1_6_1","volume-title":"Digest of Technical Papers, 1993 IEEE\/ACM International Conference on","author":"Edahiro M","year":"1993","unstructured":"Edahiro M , Delay Minimization For Zero -skew Routing, Computer-Aided Design , 1993 . ICCAD-93 . Digest of Technical Papers, 1993 IEEE\/ACM International Conference on , 1993: 563--566 Edahiro M, Delay Minimization For Zero-skew Routing, Computer-Aided Design, 1993. ICCAD-93. Digest of Technical Papers, 1993 IEEE\/ACM International Conference on, 1993: 563--566"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/567270.567271"},{"volume-title":"Proc. European Design Automation Conf","author":"Kahng A B","key":"e_1_3_2_1_8_1","unstructured":"Kahng A B , Tsao C W A , Planar - DME : Improved planar zeroskew clock routing with minimum pathlength delay , in Proc. European Design Automation Conf , 1994: 440--445 Kahng A B, Tsao C W A, Planar-DME: Improved planar zeroskew clock routing with minimum pathlength delay, in Proc. European Design Automation Conf, 1994: 440--445"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TSMCB.2003.817051"},{"issue":"1","key":"e_1_3_2_1_10_1","first-page":"73","article-title":"The development and evaluation of an improved genetic algorithm based on migration and artificial selection, Systems, Man and Cybernetics","volume":"24","author":"Potts J C","year":"1994","unstructured":"Potts J C , Giddens T D , Yadav S B , The development and evaluation of an improved genetic algorithm based on migration and artificial selection, Systems, Man and Cybernetics , IEEE Transactions on , 1994 , 24 ( 1 ): 73 -- 86 Potts J C, Giddens T D, Yadav S B, The development and evaluation of an improved genetic algorithm based on migration and artificial selection, Systems, Man and Cybernetics, IEEE Transactions on, 1994, 24 (1): 73 -- 86","journal-title":"IEEE Transactions on"},{"key":"e_1_3_2_1_11_1","volume-title":"CEC '02. Proceedings of the 2002 Congress on","author":"Ji Hun Koo","year":"2002","unstructured":"Ji Hun Koo , Tae Seon Kim, Sung Soo Dong , Chong Ho Lee, Development of FPGA based adaptive image enhancement filter system using genetic algorithms, Evolutionary , CEC '02. Proceedings of the 2002 Congress on , 2002 , 2:1480 -- 1485 Ji Hun Koo, Tae Seon Kim, Sung Soo Dong, Chong Ho Lee, Development of FPGA based adaptive image enhancement filter system using genetic algorithms, Evolutionary, CEC '02. Proceedings of the 2002 Congress on, 2002, 2:1480 -- 1485"}],"event":{"name":"GECCO05: Genetic and Evolutionary Computation Conference","sponsor":["SIGEVO ACM Special Interest Group on Genetic and Evolutionary Computation","ACM Association for Computing Machinery"],"location":"Washington DC USA","acronym":"GECCO05"},"container-title":["Proceedings of the 7th annual conference on Genetic and evolutionary computation"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1068009.1068238","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1068009.1068238","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T16:08:01Z","timestamp":1750262881000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1068009.1068238"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005,6,25]]},"references-count":11,"alternative-id":["10.1145\/1068009.1068238","10.1145\/1068009"],"URL":"https:\/\/doi.org\/10.1145\/1068009.1068238","relation":{},"subject":[],"published":{"date-parts":[[2005,6,25]]},"assertion":[{"value":"2005-06-25","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}