{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:42:34Z","timestamp":1750308154109,"version":"3.41.0"},"reference-count":12,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2005,7,1]],"date-time":"2005-07-01T00:00:00Z","timestamp":1120176000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2005,7]]},"abstract":"<jats:p>\n            The\n            <jats:italic>buffer block<\/jats:italic>\n            methodology has become increasingly popular as more and more buffers are needed in deep-submicron design, and it leads to many challenging problems in physical design. In this article, we present a polynomial-time exact algorithm for integrated pin assignment and buffer planning for all two-pin nets from one macro block (source block) to all other blocks of a given buffer block plan, while minimizing the total cost \u03b1 \u02d9\n            <jats:italic>W<\/jats:italic>\n            + \u03b2 \u02d9\n            <jats:italic>R<\/jats:italic>\n            for any positive \u03b1 and \u03b2 where\n            <jats:italic>W<\/jats:italic>\n            is the total wirelength, and\n            <jats:italic>R<\/jats:italic>\n            is the number of buffers. By applying this algorithm iteratively (each time, pick one block as the source block), it provides a polynomial-time algorithm for pin assignment and buffer planning for nets among multiple macro blocks. Experimental results demonstrate its efficiency and effectiveness.\n          <\/jats:p>","DOI":"10.1145\/1080334.1080340","type":"journal-article","created":{"date-parts":[[2005,11,7]],"date-time":"2005-11-07T16:00:45Z","timestamp":1131379245000},"page":"561-572","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["An algorithm for integrated pin assignment and buffer planning"],"prefix":"10.1145","volume":"10","author":[{"given":"Hua","family":"Xiang","sequence":"first","affiliation":[{"name":"IBM T.J. Watson Research Center, Yorktown Heights, NY"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiaoping","family":"Tang","sequence":"additional","affiliation":[{"name":"IBM T.J. Watson Research Center, Yorktown Heights, NY"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Martin D. F.","family":"Wong","sequence":"additional","affiliation":[{"name":"University of Illinois at Urbana-Champaign, Urbana, IL"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2005,7]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF01585705"},{"key":"e_1_2_1_2_1","unstructured":"Ahuja R. K. Magnanti T. L. and Orlin J. B. 1993. Network Flows. Prentice Hall. Upper Saddle River NJ.  Ahuja R. K. Magnanti T. L. and Orlin J. B. 1993. Network Flows. Prentice Hall. Upper Saddle River NJ."},{"volume-title":"Circuits, Interconnections, and Packaging for VLSI","author":"Bakoglu H. B.","key":"e_1_2_1_3_1","unstructured":"Bakoglu , H. B. 1990. Circuits, Interconnections, and Packaging for VLSI . Addison-Wesley . Bakoglu, H. B. 1990. Circuits, Interconnections, and Packaging for VLSI. Addison-Wesley."},{"key":"e_1_2_1_4_1","unstructured":"Cong J. 1997. Challenges and opportunities for design innovations in nanometer technologies. SRC Working Papers. Available at http:\/\/www.src.org\/prg_mgmt\/frontier.dgw.  Cong J. 1997. Challenges and opportunities for design innovations in nanometer technologies. SRC Working Papers. Available at http:\/\/www.src.org\/prg_mgmt\/frontier.dgw."},{"volume-title":"Proceedings of the International Conference on Computer-Aided Design (ICCAD). 358--363","author":"Cong J.","key":"e_1_2_1_5_1","unstructured":"Cong , J. , Kong , T. , and Pan , D. Z . 1999. Buffer block planning for interconnect driven floorplanning . In Proceedings of the International Conference on Computer-Aided Design (ICCAD). 358--363 . Cong, J., Kong, T., and Pan, D. Z. 1999. Buffer block planning for interconnect driven floorplanning. In Proceedings of the International Conference on Computer-Aided Design (ICCAD). 358--363."},{"key":"e_1_2_1_6_1","unstructured":"Cormen T. H. Leiserson C. E. and Rivest R. L. 1992. Introduction to Algorithms. The MIT Press Cambridge MA.   Cormen T. H. Leiserson C. E. and Rivest R. L. 1992. Introduction to Algorithms. The MIT Press Cambridge MA."},{"volume-title":"Proceedings of the International Conference on Computer-Aided Design (ICCAD'00)","author":"Dragan F. F.","key":"e_1_2_1_7_1","unstructured":"Dragan , F. F. , Kahng , A. B. , Mandoiu , I. I. , Muddu , S. , and Zelikovsky , A . 2000. Provably good global buffering using an available buffer block plan . In Proceedings of the International Conference on Computer-Aided Design (ICCAD'00) . 104--109. Dragan, F. F., Kahng, A. B., Mandoiu, I. I., Muddu, S., and Zelikovsky, A. 2000. Provably good global buffering using an available buffer block plan. In Proceedings of the International Conference on Computer-Aided Design (ICCAD'00). 104--109."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/370155.370299"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/274535.274550"},{"key":"e_1_2_1_10_1","unstructured":"Preas B. and Lorenzetti M. 1988. Physical Design Automation of VLSI Systems. Benjamin\/Cummings Menlo Park CA.  Preas B. and Lorenzetti M. 1988. Physical Design Automation of VLSI Systems. Benjamin\/Cummings Menlo Park CA."},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/332357.332398"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/332357.332397"}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1080334.1080340","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1080334.1080340","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T16:18:51Z","timestamp":1750263531000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1080334.1080340"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005,7]]},"references-count":12,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2005,7]]}},"alternative-id":["10.1145\/1080334.1080340"],"URL":"https:\/\/doi.org\/10.1145\/1080334.1080340","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"type":"print","value":"1084-4309"},{"type":"electronic","value":"1557-7309"}],"subject":[],"published":{"date-parts":[[2005,7]]},"assertion":[{"value":"2005-07-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}