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These new capabilities present both opportunities and challenges for constructing nanoscale computing systems. The tiny feature sizes offer a path to economically scale down to atomic dimensions. However, the associated bottom-up synthesis techniques only produce highly regular structures and come with high defect rates and minimal control during assembly. To exploit these technologies, we develop nanowire-based architectures which can bridge between lithographic and atomic-scale feature sizes and tolerate defective and stochastic assembly of regular arrays to deliver high density universal computing devices. Using 10nm pitch nanowires, these nanowire-based programmable architectures offer one to two orders of magnitude greater mapped-logic density than defect-free lithographic FPGAs at 22nm.<\/jats:p>","DOI":"10.1145\/1084748.1084750","type":"journal-article","created":{"date-parts":[[2005,11,7]],"date-time":"2005-11-07T16:00:45Z","timestamp":1131379245000},"page":"109-162","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":184,"title":["Nanowire-based programmable architectures"],"prefix":"10.1145","volume":"1","author":[{"given":"Andr\u00e9","family":"Dehon","sequence":"first","affiliation":[{"name":"California Institute of Technology, Pasadena, CA"}]}],"member":"320","published-online":{"date-parts":[[2005,7]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"crossref","first-page":"26","DOI":"10.1063\/1.1766071","article-title":"Fabrication of 5 nm linewidth and 14 nm pitch features by nanoimprint lithography","volume":"84","author":"Austin M. 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