{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:42:05Z","timestamp":1750308125993,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":20,"publisher":"ACM","license":[{"start":{"date-parts":[[2005,9,19]],"date-time":"2005-09-19T00:00:00Z","timestamp":1127088000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2005,9,19]]},"DOI":"10.1145\/1084834.1084878","type":"proceedings-article","created":{"date-parts":[[2005,11,7]],"date-time":"2005-11-07T17:34:39Z","timestamp":1131384879000},"page":"160-165","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["Enhanced code density of embedded CISC processors with echo technology"],"prefix":"10.1145","author":[{"given":"Youfeng","family":"Wu","sequence":"first","affiliation":[{"name":"Intel Labs, Clara, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"suffix":"Jr.","given":"Mauricio","family":"Breternitz","sequence":"additional","affiliation":[{"name":"Intel Labs, Clara, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Herbert","family":"Hum","sequence":"additional","affiliation":[{"name":"Intel Labs, Clara, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ramesh","family":"Peri","sequence":"additional","affiliation":[{"name":"Intel Labs, Clara, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jay","family":"Pickett","sequence":"additional","affiliation":[{"name":"Intel Labs, Clara, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2005,9,19]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"http:\/\/www.arm.com\/products\/CPUs\/ archi-thumb2. html","author":"ARM","year":"2004","unstructured":"ARM website , http:\/\/www.arm.com\/products\/CPUs\/ archi-thumb2. html , 2004 ARM website, http:\/\/www.arm.com\/products\/CPUs\/ archi-thumb2. html, 2004"},{"key":"e_1_3_2_1_2_1","volume-title":"March 21","author":"Brisk P.","year":"2004","unstructured":"P. Brisk and M. Sarrafzadeh , \" Framework and Design Methodology of a Compiler that Compresses Code using Echo Instructions,\" ODES-2, in conjunction with CGO04 , March 21 , 2004 P. Brisk and M. Sarrafzadeh, \"Framework and Design Methodology of a Compiler that Compresses Code using Echo Instructions,\" ODES-2, in conjunction with CGO04, March 21, 2004"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/301618.301655"},{"key":"e_1_3_2_1_4_1","volume-title":"http:\/\/sed.inf.u-szeged.hu\/csibe\/","author":"Code-Size Benchmark GCC","year":"2004","unstructured":"GCC Code-Size Benchmark Environment (CSiBE) , http:\/\/sed.inf.u-szeged.hu\/csibe\/ , 2004 GCC Code-Size Benchmark Environment (CSiBE), http:\/\/sed.inf.u-szeged.hu\/csibe\/, 2004"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/349214.349233"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/502949.502886"},{"key":"e_1_3_2_1_7_1","unstructured":"C. Fraser. \"An instruction for direct interpretation of LZ77-compressed programs \" Microsoft Technical Report MSR-TR-2002-90. ftp:\/\/ftp.research.microsoft.com\/pub\/tr\/tr-2002-90.pdf.  C. Fraser. \"An instruction for direct interpretation of LZ77-compressed programs \" Microsoft Technical Report MSR-TR-2002-90. ftp:\/\/ftp.research.microsoft.com\/pub\/tr\/tr-2002-90.pdf."},{"key":"e_1_3_2_1_8_1","unstructured":"Embedded Intel\u00ae Architecture at http:\/\/www.intel.com\/products\/embedded\/index.htm  Embedded Intel\u00ae Architecture at http:\/\/www.intel.com\/products\/embedded\/index.htm"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/513829.513840"},{"key":"e_1_3_2_1_10_1","volume-title":"Using lightweight procedures to improve instruction cache performance,\" CS-TR-99-1390","author":"Kunchithapadam K.","year":"1999","unstructured":"K. Kunchithapadam and J. Larus . \" Using lightweight procedures to improve instruction cache performance,\" CS-TR-99-1390 , University of Wisconsin , 1999 . K. Kunchithapadam and J. Larus. \"Using lightweight procedures to improve instruction cache performance,\" CS-TR-99-1390, University of Wisconsin, 1999."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.5555\/789084.789496"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/951710.951724"},{"key":"e_1_3_2_1_13_1","volume-title":"thesis","author":"Liao S.","year":"1996","unstructured":"S. Liao . \" Code Generation and Optimization for Embedded Digital Signal Processors ,\" Ph. D. thesis , 1996 . Massachusetts Institute of Technology . S. Liao. \"Code Generation and Optimization for Embedded Digital Signal Processors,\" Ph.D. thesis, 1996. Massachusetts Institute of Technology."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.5555\/1622776.1622780"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/321941.321946"},{"key":"e_1_3_2_1_16_1","unstructured":"M. Nanja and J. D. Munter \"The Effects of Compiler Optimizations and Mixed Mode Code on Application Performance Memory Footprint Power and Energy Consumption for Embedded Systems \" Submitted to CTCES04.  M. Nanja and J. D. Munter \"The Effects of Compiler Optimizations and Mixed Mode Code on Application Performance Memory Footprint Power and Energy Consumption for Embedded Systems \" Submitted to CTCES04."},{"key":"e_1_3_2_1_17_1","unstructured":"National Geode x86 \"appliance-on-chip\" SOCs http: \/\/www.linuxdevices.com\/products\/PD6094486551.html  National Geode x86 \"appliance-on-chip\" SOCs http: \/\/www.linuxdevices.com\/products\/PD6094486551.html"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"crossref","unstructured":"E. Ukkonen \"On-line construction of suffix trees \" Algorithmica Sept 1995.  E. Ukkonen \"On-line construction of suffix trees \" Algorithmica Sept 1995.","DOI":"10.1007\/BF01206331"},{"key":"e_1_3_2_1_19_1","unstructured":"Via Embedded Platforms at http:\/\/www.viaembedded.com\/index.jsp.  Via Embedded Platforms at http:\/\/www.viaembedded.com\/index.jsp."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.1977.1055714"}],"event":{"name":"CODES\/ISSS05: Third IEEE\/ACM\/IFIP International Conference on Hardware\/Software Codesign and System Synthesis","sponsor":["ACM Association for Computing Machinery","SIGBED ACM Special Interest Group on Embedded Systems","SIGDA ACM Special Interest Group on Design Automation"],"location":"Jersey City NJ USA","acronym":"CODES\/ISSS05"},"container-title":["Proceedings of the 3rd IEEE\/ACM\/IFIP international conference on Hardware\/software codesign and system synthesis"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1084834.1084878","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1084834.1084878","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T16:08:24Z","timestamp":1750262904000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1084834.1084878"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005,9,19]]},"references-count":20,"alternative-id":["10.1145\/1084834.1084878","10.1145\/1084834"],"URL":"https:\/\/doi.org\/10.1145\/1084834.1084878","relation":{},"subject":[],"published":{"date-parts":[[2005,9,19]]},"assertion":[{"value":"2005-09-19","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}