{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:41:52Z","timestamp":1750308112582,"version":"3.41.0"},"reference-count":30,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2005,8,1]],"date-time":"2005-08-01T00:00:00Z","timestamp":1122854400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2005,8]]},"abstract":"<jats:p>UCLA teaches students how to master the steep slopes of the embedded systems mountain. The EE201A graduate course connects high-level design specification to embedded implementation. There is a long-standing and wide culture gap between system designers that create those abstract specifications and the system architects that need to implement them. In industry, the culture gap has separated software from hardware teams, and platform creators from platform users. In an embedded context, where these are very tightly connected, this leads to large inefficiencies both in design time and design results. Our course takes students to both sides of the gap and lets them look at this problem from different perspectives. For a given application, it teaches how to select target architectures, tools, and design methods. The course covers a stepwise systematic design process. It includes specification, transformation, and refinement of an application. Specifications enable systematic and structured expression of an application. Transformations rework specifications into ones that are a better match for a given target architecture. Refinements lower the abstraction level toward the target architecture. The embedded systems mountain is traversed in two directions. A vertical refinement axis covers elements such as power-memory-reduction methods or fixed-point refinement. A horizontal exploration axis covers various architecture alternatives including application-specific integrated circuits (ASIC), domain-specific processors, digital signal processors (DSP), embedded cores, programmable processors, and system-on-chip (SOC). During the course, the students also go through an extensive design project to apply the methods learned in this course. A typical embedded application is used to drive the project. In this paper it is illustrated using an embedded version of an image encoder, more specifically a JPEG encoder. Several commercial tools, design environments, and platforms have been used as alternative implementation targets for this application.<\/jats:p>","DOI":"10.1145\/1086519.1086523","type":"journal-article","created":{"date-parts":[[2005,11,7]],"date-time":"2005-11-07T16:00:45Z","timestamp":1131379245000},"page":"529-548","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["Skiing the embedded systems mountain"],"prefix":"10.1145","volume":"4","author":[{"given":"Ingrid","family":"Verbauwhede","sequence":"first","affiliation":[{"name":"University of California at Los Angeles and Katholieke Universiteit Leuven, Belgium"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Patrick","family":"Schaumont","sequence":"additional","affiliation":[{"name":"University of California at Los Angeles, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2005,8]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"ARM OptimoDE. 2004. (http:\/\/www.arm.com\/products\/CPUs\/families\/OptimoDE.html) OptimoDE Data Engine Family.  ARM OptimoDE. 2004. (http:\/\/www.arm.com\/products\/CPUs\/families\/OptimoDE.html) OptimoDE Data Engine Family."},{"key":"e_1_2_1_2_1","series-title":"Article series","volume-title":"Under the hood. Electronic Engineering Times","author":"Carey D.","unstructured":"Carey , D. 2004. (http:\/\/www.eet.com\/sys\/uth\/) , Under the hood. Electronic Engineering Times , Article series . Carey, D. 2004. (http:\/\/www.eet.com\/sys\/uth\/), Under the hood. Electronic Engineering Times, Article series."},{"key":"e_1_2_1_3_1","doi-asserted-by":"crossref","unstructured":"Catthoor F. Wuytack S. De Greef E. Balasa F. Nachtergaele L. and Vandecappelle A. 1998. Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design. Kluwer Academic Publ. Boston MA.   Catthoor F. Wuytack S. De Greef E. Balasa F. Nachtergaele L. and Vandecappelle A. 1998. Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design. Kluwer Academic Publ. Boston MA.","DOI":"10.1007\/978-1-4757-2849-1"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCOM.1977.1093941"},{"volume-title":"Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'99)","author":"Cmar R.","key":"e_1_2_1_5_1","unstructured":"Cmar , R. , Rijnders , L. , Schaumont , P. , Vernalde , S. , and Bolsens , I . 1999. A methodology and design environment for DSP ASIC fixed point refinement . In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'99) . 271--276. 10.1145\/307418.307503 Cmar, R., Rijnders, L., Schaumont, P., Vernalde, S., and Bolsens, I. 1999. A methodology and design environment for DSP ASIC fixed point refinement. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'99). 271--276. 10.1145\/307418.307503"},{"key":"e_1_2_1_6_1","volume-title":"Proceedings European Solid-State Circuits Conference (ESSCIRC'02)","author":"De Man H.","year":"2002","unstructured":"De Man , H. 2002 . Nanoscale system design challenges: Business as usual? In Proceedings European Solid-State Circuits Conference (ESSCIRC'02) . 3--10. De Man, H. 2002. Nanoscale system design challenges: Business as usual? In Proceedings European Solid-State Circuits Conference (ESSCIRC'02). 3--10."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.1983.1654264"},{"key":"e_1_2_1_8_1","doi-asserted-by":"crossref","unstructured":"Gajski D. Zhu J. Domer R. Gerstlauer A. and Zhao S. 2000. SpecC Specification language and design methodology. Kluwer Academic Publishers Boston MA.  Gajski D. Zhu J. Domer R. Gerstlauer A. and Zhao S. 2000. SpecC Specification language and design methodology. Kluwer Academic Publishers Boston MA.","DOI":"10.1007\/978-1-4615-4515-6"},{"key":"e_1_2_1_9_1","unstructured":"Gerstlauer A. 2004. (http:\/\/www.ics.uci.edu\/~specc) The SpecC System.  Gerstlauer A. 2004. (http:\/\/www.ics.uci.edu\/~specc) The SpecC System."},{"key":"e_1_2_1_10_1","unstructured":"Gezel Homepage. 2004. (http:\/\/www.ee.ucla.edu\/~schaum\/gezel).  Gezel Homepage. 2004. (http:\/\/www.ee.ucla.edu\/~schaum\/gezel)."},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2003.1212696"},{"key":"e_1_2_1_12_1","doi-asserted-by":"crossref","unstructured":"Hoffmann A. Leupers R. and Meyr H. 2002. Architecture exploration for embedded processors with LISA. Kluwer Academic Publishers Boston MA.   Hoffmann A. Leupers R. and Meyr H. 2002. Architecture exploration for embedded processors with LISA. Kluwer Academic Publishers Boston MA.","DOI":"10.1007\/978-1-4757-4538-2"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1016\/0167-6423(87)90035-9"},{"key":"e_1_2_1_14_1","unstructured":"Imec 2004. (http:\/\/www.imec.be\/design\/atomium) Welcome to the Atomium project.  Imec 2004. (http:\/\/www.imec.be\/design\/atomium) Welcome to the Atomium project."},{"key":"e_1_2_1_15_1","unstructured":"ITRS 2003. (http:\/\/public.itrs.net\/Files\/2003ITRS\/Home2003.htm) International Technology Roadmap for Semiconductors.  ITRS 2003. (http:\/\/public.itrs.net\/Files\/2003ITRS\/Home2003.htm) International Technology Roadmap for Semiconductors."},{"volume-title":"Proceedings of the Design, Automation and Test in Europe. 429--435","author":"Keding H.","key":"e_1_2_1_16_1","unstructured":"Keding , H. , Willems , M. , Coors , M. , and Meyr , H . 1998. FRIDGE: a fixed-point design and simulation environment . In Proceedings of the Design, Automation and Test in Europe. 429--435 . Keding, H., Willems, M., Coors, M., and Meyr, H. 1998. FRIDGE: a fixed-point design and simulation environment. In Proceedings of the Design, Automation and Test in Europe. 429--435."},{"key":"e_1_2_1_17_1","unstructured":"Lee E. and Sangiovanni-Vincentelli A. 1996. The tagged signal model---a preliminary version of a denotational framework for comparing models of computation. Memorandum UCB\/ERL M96\/33 EECS UC Berkeley CA.  Lee E. and Sangiovanni-Vincentelli A. 1996. The tagged signal model---a preliminary version of a denotational framework for comparing models of computation. Memorandum UCB\/ERL M96\/33 EECS UC Berkeley CA."},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1987.13876"},{"key":"e_1_2_1_19_1","unstructured":"McCanne S. and Jacobson V. 1995. vic: A Flexible framework for packet video. ACM Multimedia 1995. 10.1145\/217279.215315   McCanne S. and Jacobson V. 1995. vic: A Flexible framework for packet video. ACM Multimedia 1995. 10.1145\/217279.215315"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/375977.375978"},{"key":"e_1_2_1_21_1","volume-title":"VLSI Digital Signal Processing Systems: Design and Implementation","author":"Parhi K.","year":"1999","unstructured":"Parhi , K. 1999. VLSI Digital Signal Processing Systems: Design and Implementation . Wiley , New York , 1999 . Parhi, K. 1999. VLSI Digital Signal Processing Systems: Design and Implementation. Wiley, New York, 1999."},{"key":"e_1_2_1_22_1","doi-asserted-by":"crossref","unstructured":"Pennebaker W. and Mitchell J. 1992. JPEG Still Image Data Compression Standard. Kluwer Academic Publishers Boston MA.   Pennebaker W. and Mitchell J. 1992. JPEG Still Image Data Compression Standard. Kluwer Academic Publishers Boston MA.","DOI":"10.1117\/12.48892"},{"volume-title":"Engineering the Complex SoC","author":"Rowen C.","key":"e_1_2_1_23_1","unstructured":"Rowen , C. 2004. Engineering the Complex SoC . Prentice-Hall PTR , Upper Saddle River, NJ 07458. Rowen, C. 2004. Engineering the Complex SoC. Prentice-Hall PTR, Upper Saddle River, NJ 07458."},{"key":"e_1_2_1_24_1","volume-title":"Asia and South Pacific Design Automation Conference (ASP-DAC'03)","author":"Sakiyama K.","year":"1977","unstructured":"Sakiyama , K. , Schaumont , P. , and Verbauwhede , I . 2003a. Finding the best system design flow for a high-speed JPEG encoder . Asia and South Pacific Design Automation Conference (ASP-DAC'03) , ( Jan. ). 10.1145\/11 1977 2.1119899 Sakiyama, K., Schaumont, P., and Verbauwhede, I. 2003a. Finding the best system design flow for a high-speed JPEG encoder. Asia and South Pacific Design Automation Conference (ASP-DAC'03), (Jan.). 10.1145\/1119772.1119899"},{"volume-title":"Proceedings IEEE International Conference on Microelectronics Systems Education (MSE'03)","author":"Sakiyama K.","key":"e_1_2_1_25_1","unstructured":"Sakiyama , K. , Schaumont , P. , Hwang , D. , and Verbauwhede , I . 2003b. Teaching trade-offs in system-level design methodologies . In Proceedings IEEE International Conference on Microelectronics Systems Education (MSE'03) . 62--63. Sakiyama, K., Schaumont, P., Hwang, D., and Verbauwhede, I. 2003b. Teaching trade-offs in system-level design methodologies. In Proceedings IEEE International Conference on Microelectronics Systems Education (MSE'03). 62--63."},{"volume-title":"38th IEEE\/ACM Design Automation Conference (DAC'01)","author":"Schaumont P.","key":"e_1_2_1_26_1","unstructured":"Schaumont , P. , Verbauwhede , I. , Keutzer , K. , and Sarrafzadeh , M . 2001. A quick safari through the reconfiguration jungle . In 38th IEEE\/ACM Design Automation Conference (DAC'01) . 172--177. 10.1145\/378239.378404 Schaumont, P., Verbauwhede, I., Keutzer, K., and Sarrafzadeh, M. 2001. A quick safari through the reconfiguration jungle. In 38th IEEE\/ACM Design Automation Conference (DAC'01). 172--177. 10.1145\/378239.378404"},{"volume-title":"Digital signal processing, the new semiconductor industry technology driver","author":"Strauss W.","key":"e_1_2_1_27_1","unstructured":"Strauss , W. 2000. Digital signal processing, the new semiconductor industry technology driver . IEEE Signal Processing Magazine (Mar .), 52--56. Strauss, W. 2000. Digital signal processing, the new semiconductor industry technology driver. IEEE Signal Processing Magazine (Mar.), 52--56."},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/78.553544"},{"volume-title":"2000 IEEE\/ACM international symposium on low power electronics and design (ISLPED'00)","author":"Verbauwhede I.","key":"e_1_2_1_29_1","unstructured":"Verbauwhede , I. and Nicol , C . 2000. Low power DSP's for wireless communications . In 2000 IEEE\/ACM international symposium on low power electronics and design (ISLPED'00) . 303--310. 10.1145\/344166.344647 Verbauwhede, I. and Nicol, C. 2000. Low power DSP's for wireless communications. In 2000 IEEE\/ACM international symposium on low power electronics and design (ISLPED'00). 303--310. 10.1145\/344166.344647"},{"key":"e_1_2_1_30_1","first-page":"10","article-title":"A Two-Stage approach to multidimensional periodic scheduling","volume":"20","author":"Verhaegh W.","year":"2001","unstructured":"Verhaegh , W. , Aarts , E. , van Gorp , P. , and Lippens , P. 2001 . A Two-Stage approach to multidimensional periodic scheduling . IEEE Transactions on CAD 20 , 10 (Oct.). Verhaegh, W., Aarts, E., van Gorp, P., and Lippens, P. 2001. A Two-Stage approach to multidimensional periodic scheduling. IEEE Transactions on CAD 20, 10 (Oct.).","journal-title":"IEEE Transactions on CAD"}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1086519.1086523","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1086519.1086523","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T16:08:12Z","timestamp":1750262892000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1086519.1086523"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005,8]]},"references-count":30,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2005,8]]}},"alternative-id":["10.1145\/1086519.1086523"],"URL":"https:\/\/doi.org\/10.1145\/1086519.1086523","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"type":"print","value":"1539-9087"},{"type":"electronic","value":"1558-3465"}],"subject":[],"published":{"date-parts":[[2005,8]]},"assertion":[{"value":"2005-08-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}