{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:42:01Z","timestamp":1750308121073,"version":"3.41.0"},"reference-count":25,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2005,9,1]],"date-time":"2005-09-01T00:00:00Z","timestamp":1125532800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2005,9]]},"abstract":"<jats:p>\n            Thread-Level Speculation (TLS) provides architectural support to aggressively run hard-to-analyze code in parallel. As speculative tasks run concurrently, they generate unsafe or speculative\n            <jats:italic>memory state<\/jats:italic>\n            that needs to be separately buffered and managed in the presence of distributed caches and buffers. Such a state may contain multiple versions of the same variable. In this paper, we introduce a novel taxonomy of approaches to buffer and manage multiversion speculative memory state in multiprocessors. We also present a detailed complexity-benefit tradeoff analysis of the different approaches. Finally, we use numerical applications to evaluate the performance of the approaches under a single architectural framework. Our key insights are that support for buffering the state of multiple speculative tasks and versions per processor is more complexity-effective than support for lazily merging the state of tasks with main memory. Moreover, both supports can be gainfully combined and, in large machines, their effect is nearly fully additive. Finally, the more complex support for storing future state in the main memory can boost performance when buffers are under pressure, but hurts performance when squashes are frequent.\n          <\/jats:p>","DOI":"10.1145\/1089008.1089010","type":"journal-article","created":{"date-parts":[[2005,11,7]],"date-time":"2005-11-07T16:00:45Z","timestamp":1131379245000},"page":"247-279","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":23,"title":["Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors"],"prefix":"10.1145","volume":"2","author":[{"given":"Mar\u00eda Jes\u00fas","family":"Garzar\u00e1n","sequence":"first","affiliation":[{"name":"University of Illinois at Urbana-Champaign, Urbana, IL"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Milos","family":"Prvulovic","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jos\u00e9 Mar\u00eda","family":"Llaber\u00eda","sequence":"additional","affiliation":[{"name":"Universitat Polit\u00e8cnica de Catalunya, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"V\u00edctor","family":"Vi\u00f1als","sequence":"additional","affiliation":[{"name":"Universidad de Zaragoza, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lawrence","family":"Rauchwerger","sequence":"additional","affiliation":[{"name":"Texas A&amp;M University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Josep","family":"Torrellas","sequence":"additional","affiliation":[{"name":"University of Illinois at Urbana-Champaign, Urbana, IL"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2005,9]]},"reference":[{"volume-title":"International Symposium on Microarchitecture. 226--236","author":"Akkary H.","key":"e_1_2_1_1_1","unstructured":"Akkary , H. and Driscoll , M. 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In Proceeding of the International Conference on Parallel Architectures and Compilation Techniques. 170--181 . Garzar\u00e1n, M. J., Prvulovic, M., Llaber\u00eda, J. M., Vi\u00f1als, V., Rauchwerger, L., and Torrellas, J. 2003. Using software logging to support multi-version buffering in thread-level speculation. In Proceeding of the International Conference on Parallel Architectures and Compilation Techniques. 170--181."},{"volume-title":"Proceedings of the 4th International Symposium on High-Performance Computer Architecture. 195--205","author":"Gopal S.","key":"e_1_2_1_10_1","unstructured":"Gopal , S. , Vijaykumar , T. N. , Smith , J. E. , and Sohi , G. S . 1998. Speculative versioning cache . In Proceedings of the 4th International Symposium on High-Performance Computer Architecture. 195--205 . Gopal, S., Vijaykumar, T. N., Smith, J. E., and Sohi, G. S. 1998. Speculative versioning cache. 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