{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,26]],"date-time":"2026-02-26T11:55:02Z","timestamp":1772106902912,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":36,"publisher":"ACM","license":[{"start":{"date-parts":[[2005,10,26]],"date-time":"2005-10-26T00:00:00Z","timestamp":1130284800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2005,10,26]]},"DOI":"10.1145\/1095890.1095915","type":"proceedings-article","created":{"date-parts":[[2005,11,7]],"date-time":"2005-11-07T17:34:39Z","timestamp":1131384879000},"page":"173-182","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":77,"title":["Design and analysis of an NoC architecture from performance, reliability and energy perspective"],"prefix":"10.1145","author":[{"given":"Jongman","family":"Kim","sequence":"first","affiliation":[{"name":"Pennsylvania State University, University Park, PA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dongkook","family":"Park","sequence":"additional","affiliation":[{"name":"Pennsylvania State University, University Park, PA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chrysostomos","family":"Nicopoulos","sequence":"additional","affiliation":[{"name":"Pennsylvania State University, University Park, PA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"N.","family":"Vijaykrishnan","sequence":"additional","affiliation":[{"name":"Pennsylvania State University, University Park, PA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chita R.","family":"Das","sequence":"additional","affiliation":[{"name":"Pennsylvania State University, University Park, PA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2005,10,26]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"On-chip Micro-network. In Proceedings of the DATE","author":"Adriahantenaina A.","year":"2003","unstructured":"A. Adriahantenaina , H. Charlery , A. Greiner , L. Moriiez , and C. A. Zeferino . SPIN: A Scalable, Packet Switched , On-chip Micro-network. In Proceedings of the DATE , 2003 . A. Adriahantenaina, H. Charlery, A. Greiner, L. Moriiez, and C. A. Zeferino. SPIN: A Scalable, Packet Switched, On-chip Micro-network. In Proceedings of the DATE, 2003."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/71.97897"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/343647.343863"},{"key":"e_1_3_2_1_4_1","first-page":"1485","volume-title":"Parallel and Distributed Processing Techniques and Applications (PDPTA'02)","author":"Baker J. M.","year":"2002","unstructured":"J. M. Baker , S. B. Jr., M. Bucciero , B. Gold , and R. Mahajan . SCMP: A Single-Chip Message Passing Parallel Computer . In Parallel and Distributed Processing Techniques and Applications (PDPTA'02) , pages 1485 -- 1491 , 2002 . J. M. Baker, S. B. Jr., M. Bucciero, B. Gold, and R. Mahajan. SCMP: A Single-Chip Message Passing Parallel Computer. In Parallel and Distributed Processing Techniques and Applications (PDPTA'02), pages 1485--1491, 2002."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.5555\/882452.874339"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.5555\/882452.874339"},{"key":"e_1_3_2_1_8_1","first-page":"56","volume-title":"Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Designs. In International Conference on Computer-Aided Design","author":"Cao Y.","year":"2000","unstructured":"Y. Cao , C. Hu , A. B. Kahng , S. Muddu , D. Stroobandt , and D. Sylvester . Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Designs. In International Conference on Computer-Aided Design , pages 56 -- 61 , 2000 . Y. Cao, C. Hu, A. B. Kahng, S. Muddu, D. Stroobandt, and D. Sylvester. Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Designs. In International Conference on Computer-Aided Design, pages 56--61, 2000."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379048"},{"key":"e_1_3_2_1_10_1","volume-title":"Morgan Kaufmann","author":"Dally W. J.","year":"2003","unstructured":"W. J. Dally and B. Towles . Principles and Practices of Interconnection Networks . Morgan Kaufmann , 2003 . W. J. Dally and B. Towles. Principles and Practices of Interconnection Networks. Morgan Kaufmann, 2003."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1119772.1119817"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1023833.1023849"},{"key":"e_1_3_2_1_13_1","volume-title":"Proc. of the IEEE NorChip Conference","author":"A.","year":"2000","unstructured":"A. H. et al. Network on a Chip: An Architecture for Billion Transistor Era . In Proc. of the IEEE NorChip Conference , November 2000 . A. H. et al. Network on a Chip: An Architecture for Billion Transistor Era. In Proc. of the IEEE NorChip Conference, November 2000."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.612211"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.920580"},{"key":"e_1_3_2_1_16_1","volume-title":"Proc. Design, Automation and Test in Europe Conference","author":"Hu J.","year":"2003","unstructured":"J. Hu and R. Marculescu . Exploiting the Routing Flexibility for Energy\/Performance Aware Mapping of Regular NoC Architectures . In Proc. Design, Automation and Test in Europe Conference , 2003 . J. Hu and R. Marculescu. Exploiting the Routing Flexibility for Energy\/Performance Aware Mapping of Regular NoC Architectures. In Proc. Design, Automation and Test in Europe Conference, 2003."},{"key":"e_1_3_2_1_17_1","volume-title":"Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT)","author":"Huh J.","year":"2001","unstructured":"J. Huh , S. W. Keckler , and D. Burger . Exploring the Design Space of Future CMPs . In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT) , 2001 . J. Huh, S. W. Keckler, and D. Burger. Exploring the Design Space of Future CMPs. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT), 2001."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1119772.1119818"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"crossref","first-page":"36","DOI":"10.1109\/NCA.2001.962514","volume-title":"NCA '01: Proceedings of the IEEE International Symposium on Network Computing and Applications (NCA'01)","author":"Jung E.","year":"2001","unstructured":"E. Jung , K. K. H. Yum , and C. R. Das . Calculation of deadline missing probability in a qos capable cluster interconnect . In NCA '01: Proceedings of the IEEE International Symposium on Network Computing and Applications (NCA'01) , page 36 , Washington, DC, USA , 2001 . IEEE Computer Society. E. Jung, K. K. H. Yum, and C. R. Das. Calculation of deadline missing probability in a qos capable cluster interconnect. In NCA '01: Proceedings of the IEEE International Symposium on Network Computing and Applications (NCA'01), page 36, Washington, DC, USA, 2001. IEEE Computer Society."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065726"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.913759"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.5555\/876908.881610"},{"key":"e_1_3_2_1_23_1","first-page":"524","volume-title":"Single-Chip Communications Architecture. In the IEEE International Conference on Parallel Architectures and Compilation Techniques","author":"Liang J.","year":"2000","unstructured":"J. Liang , S. Swaminathan , and R. Tessier . aSOC: A Scalable , Single-Chip Communications Architecture. In the IEEE International Conference on Parallel Architectures and Compilation Techniques , pages 524 -- 529 , October 2000 . J. Liang, S. Swaminathan, and R. Tessier. aSOC: A Scalable, Single-Chip Communications Architecture. In the IEEE International Conference on Parallel Architectures and Compilation Techniques, pages 524--529, October 2000."},{"key":"e_1_3_2_1_24_1","volume-title":"Networks-On-Chip: The Quest for On-Chip Fault-Tolerant Communication. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)","author":"Marculescu R.","year":"2003","unstructured":"R. Marculescu . Networks-On-Chip: The Quest for On-Chip Fault-Tolerant Communication. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03) , 2003 . R. Marculescu. Networks-On-Chip: The Quest for On-Chip Fault-Tolerant Communication. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03), 2003."},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/71.940747"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/775832.776059"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1014984417525"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.5555\/822080.822800"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.5555\/244522.244879"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.5555\/647883.738394"},{"key":"e_1_3_2_1_31_1","unstructured":"Sonics Incorporated. http:\/\/www.sonicsinc.com.  Sonics Incorporated. http:\/\/www.sonicsinc.com."},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996600"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/988952.988964"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.5555\/789083.1022750"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.5555\/554220.838064"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/944645.944694"}],"event":{"name":"ANCS05: Symposium on Architecture for Networking and Communications Systems 2005","location":"Princeton NJ USA","acronym":"ANCS05","sponsor":["SIGCOMM ACM Special Interest Group on Data Communication","ACM Association for Computing Machinery","SIGARCH ACM Special Interest Group on Computer Architecture"]},"container-title":["Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1095890.1095915","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1095890.1095915","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T16:18:54Z","timestamp":1750263534000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1095890.1095915"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005,10,26]]},"references-count":36,"alternative-id":["10.1145\/1095890.1095915","10.1145\/1095890"],"URL":"https:\/\/doi.org\/10.1145\/1095890.1095915","relation":{},"subject":[],"published":{"date-parts":[[2005,10,26]]},"assertion":[{"value":"2005-10-26","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}