{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:41:39Z","timestamp":1750308099438,"version":"3.41.0"},"reference-count":16,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2004,9,29]],"date-time":"2004-09-29T00:00:00Z","timestamp":1096416000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGARCH Comput. Archit. News"],"published-print":{"date-parts":[[2005,6]]},"abstract":"<jats:p>In the context of battery-driven embedded systems, reducing energy while maintaining performance is one of today's challenges. The on-chip memory count for a great part of the whole system consumption, especially for images and video processing applications that make heavy use of large memory data size.In this paper, we present new technique for efficiently exploiting on-chip memory space (cache, scrathpad) for a specific application to reduce the energy consumption without loss of performance. We configure and compare the impact of three different memory architectures on the energy consumption. The first one is composed of main memory with cache, in the second architecture we find a main memory and scratchpad memory and in the last architecture we combine both cache and scratchpad with the main memory. We show the effectiveness of the last architecture and a saving about 35% in energy consumption.<\/jats:p>","DOI":"10.1145\/1101868.1101871","type":"journal-article","created":{"date-parts":[[2006,2,6]],"date-time":"2006-02-06T18:14:10Z","timestamp":1139249650000},"page":"3-9","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["Energy aware memory architecture configuration"],"prefix":"10.1145","volume":"33","author":[{"given":"Hanene Ben","family":"Fradj","sequence":"first","affiliation":[{"name":"Laboratoire d'Informatique, signaux et Syst\u00e8mes de Sophia-Antipolis, Sophia-Antipos Cedex, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Asmaa","family":"el Ouardighi","sequence":"additional","affiliation":[{"name":"Laboratoire d'Informatique, signaux et Syst\u00e8mes de Sophia-Antipolis, Sophia-Antipos Cedex, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"C\u00e9cile","family":"Belleudy","sequence":"additional","affiliation":[{"name":"Laboratoire d'Informatique, signaux et Syst\u00e8mes de Sophia-Antipolis, Sophia-Antipos Cedex, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michel","family":"Auguin","sequence":"additional","affiliation":[{"name":"Laboratoire d'Informatique, signaux et Syst\u00e8mes de Sophia-Antipolis, Sophia-Antipos Cedex, France"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2004,9,29]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Workshop on VLSI Signal Processing","author":"Catthoor F.","year":"1994","unstructured":"F. Catthoor , F. Franssen , S. Wuytack , L. Nachtergaele , H. De Man , \"Global Communication and Memory Optimizing Transformations for Low Power Signal Processing Systems\" , Workshop on VLSI Signal Processing , Oct 1994 . F. Catthoor, F. Franssen, S. Wuytack, L. Nachtergaele, H. De Man, \"Global Communication and Memory Optimizing Transformations for Low Power Signal Processing Systems\", Workshop on VLSI Signal Processing, Oct 1994."},{"key":"e_1_2_1_2_1","volume-title":"Technical Repport, Compaq, Western Reaserch Laboratory, august","author":"Shivakumar N.","year":"2001","unstructured":"P. Shivakumar , N. Jouppi , \"Cacti 3. 0 : An Integrted Cache Timing, Power and Area Model \", Technical Repport, Compaq, Western Reaserch Laboratory, august 2001 . P. Shivakumar, N. Jouppi, \"Cacti 3.0: An Integrted Cache Timing, Power and Area Model\", Technical Repport, Compaq, Western Reaserch Laboratory, august 2001."},{"key":"e_1_2_1_3_1","first-page":"261","volume-title":"a comparative study \"in Proc","author":"Kamble K.","year":"1997","unstructured":"M. Kamble , K. Ghose \"Energy-Efficient of VLSI caches : a comparative study \"in Proc . IEEE 10 th International Conference on VLSI Design, pp. 261 -- 267 , Junuary 1997 M. Kamble, K. Ghose \"Energy-Efficient of VLSI caches: a comparative study \"in Proc. IEEE 10 th International Conference on VLSI Design, pp. 261--267, Junuary 1997"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/224081.224093"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/309847.309902"},{"key":"e_1_2_1_6_1","volume-title":"Univertsit\u00e9 of Dortmund","author":"Banakar S.","year":"2001","unstructured":"R. Banakar , S. Steinke , B. Lee , M. Balakrishnana , P. Marwedel \"Comparaison of Cache and Scratch-Pad based Memory Sytems with respect to Perfermance, Area and Energy Consumption\". Technical Repport 762 , Univertsit\u00e9 of Dortmund , September 2001 . R. Banakar, S. Steinke, B. Lee, M. Balakrishnana, P. Marwedel \"Comparaison of Cache and Scratch-Pad based Memory Sytems with respect to Perfermance, Area and Energy Consumption\". Technical Repport 762, Univertsit\u00e9 of Dortmund, September 2001."},{"key":"e_1_2_1_7_1","volume-title":"june","author":"Zhang C.","year":"2003","unstructured":"Zhang , C. , Vahid , F. \" Cache configuration exploration on prototyping platforms\" 14th IEEE international workshop on rapid systems prototyping , june 2003 . Zhang, C., Vahid, F. \"Cache configuration exploration on prototyping platforms\" 14th IEEE international workshop on rapid systems prototyping, june 2003."},{"key":"e_1_2_1_8_1","unstructured":"Ann Gordon-ross Frank Vahid Nikil Dutt \"Automatic timing of two level caches to embedded applications\" DATE France 2004.   Ann Gordon-ross Frank Vahid Nikil Dutt \"Automatic timing of two level caches to embedded applications\" DATE France 2004."},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859635"},{"key":"e_1_2_1_10_1","unstructured":"Nathalie Julien \"M\u00e9thodes de conception faible consommation des circuits VLSI Habilitation \u00e0 diriger des recherche en science pour l'ing\u00e9nieur p 36.  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Suytack \"Custom memory management methodology: Exploration of memory organisation for embeddede multimedia system design\" Kluwer academic publisher 1998 ISBN 0-79238288-9."},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/552726"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.5555\/1068504.1068748"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/321738.321743"},{"key":"e_1_2_1_16_1","volume-title":"DATE","author":"Verma L.","year":"2004","unstructured":"M. Verma , L. Wehmeyer , P. Marwedel \"Cache-Aware Scratchpad Allocation Algorithm\" DATE 2004 , Paris, France. M. Verma, L. Wehmeyer, P. Marwedel \"Cache-Aware Scratchpad Allocation Algorithm\" DATE 2004, Paris, France."}],"container-title":["ACM SIGARCH Computer Architecture News"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1101868.1101871","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1101868.1101871","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T16:08:01Z","timestamp":1750262881000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1101868.1101871"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2004,9,29]]},"references-count":16,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2005,6]]}},"alternative-id":["10.1145\/1101868.1101871"],"URL":"https:\/\/doi.org\/10.1145\/1101868.1101871","relation":{"is-identical-to":[{"id-type":"doi","id":"10.1145\/1152922.1101871","asserted-by":"subject"}]},"ISSN":["0163-5964"],"issn-type":[{"type":"print","value":"0163-5964"}],"subject":[],"published":{"date-parts":[[2004,9,29]]},"assertion":[{"value":"2004-09-29","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}