{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:41:39Z","timestamp":1750308099274,"version":"3.41.0"},"reference-count":13,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2004,9,29]],"date-time":"2004-09-29T00:00:00Z","timestamp":1096416000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGARCH Comput. Archit. News"],"published-print":{"date-parts":[[2005,6]]},"abstract":"<jats:p>A SuperH\u2122 embedded processor core SH-X implemented in a 130-nm CMOS process running at 400 MHz achieved 720 MIPS and 2.8 GFLOPS at a power of 250 mW under worst-case conditions. It has a dual-issue seven-stage pipeline architecture, but reaches the 1.8 MIPS\/MHz of the previous five-stage processor. The on-chip memory configuration is tuned for digital consumer appliances. A new resume-standby mode enables a standby current of less than 100, \u03bcA and a 3-ms recovery time. The processor meets the requirements of a wide range of applications, and is suitable for digital appliances aimed at the consumer market, such as cellular phones, digital still\/video cameras, and car navigation systems.<\/jats:p>","DOI":"10.1145\/1101868.1101875","type":"journal-article","created":{"date-parts":[[2006,2,6]],"date-time":"2006-02-06T18:14:10Z","timestamp":1139249650000},"page":"33-40","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["SH-X"],"prefix":"10.1145","volume":"33","author":[{"given":"F.","family":"Arakawa","sequence":"first","affiliation":[{"name":"Hitachi Ltd., Central Research Laboratory, Tokyo Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Ishikawa","sequence":"additional","affiliation":[{"name":"Hitachi Ltd., Central Research Laboratory, Tokyo Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Y.","family":"Kondo","sequence":"additional","affiliation":[{"name":"Hitachi Ltd., Central Research Laboratory, Tokyo Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"T.","family":"Kamei","sequence":"additional","affiliation":[{"name":"Renesas Technology Corporation, Tokyo Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Ozawa","sequence":"additional","affiliation":[{"name":"Hitachi Ltd., Central Research Laboratory, Tokyo Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"O.","family":"Nishii","sequence":"additional","affiliation":[{"name":"SuperH (Japan), Ltd., Tokyo Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"T.","family":"Hattori","sequence":"additional","affiliation":[{"name":"SuperH (Japan), Ltd., Tokyo Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2004,9,29]]},"reference":[{"key":"e_1_2_1_1_1","first-page":"370","article-title":"A 133MHz 170mW 10&mu;A Standby Application Processor for 3G Cellular Phones","author":"Yamada T.","year":"2002","unstructured":"T. Yamada , \" A 133MHz 170mW 10&mu;A Standby Application Processor for 3G Cellular Phones ,\" ISSCC Dig. Tech. Papers , pp. 370 -- 371 , 474, Feb. 2002 . T. Yamada et al., \"A 133MHz 170mW 10&mu;A Standby Application Processor for 3G Cellular Phones,\" ISSCC Dig. Tech. Papers, pp. 370--371, 474, Feb. 2002.","journal-title":"ISSCC Dig. Tech. Papers"},{"key":"e_1_2_1_2_1","first-page":"2","article-title":"A Low-Power Embedded RISC Microprocessor with an Integrated DSP for Mobile Applications","volume":"85","author":"Yamada T.","year":"2002","unstructured":"T. Yamada , \" A Low-Power Embedded RISC Microprocessor with an Integrated DSP for Mobile Applications ,\" IEICE Transactions , Vol. E85 -C No. 2 , pp. 253--262, Feb. 2002 . T. Yamada et al., \"A Low-Power Embedded RISC Microprocessor with an Integrated DSP for Mobile Applications,\" IEICE Transactions, Vol. E85-C No. 2, pp. 253--262, Feb. 2002.","journal-title":"IEICE Transactions"},{"key":"e_1_2_1_3_1","first-page":"102","article-title":"Application Processor for 3G Cellular Phones","author":"Tsunoda T.","year":"2002","unstructured":"T. Tsunoda , \" Application Processor for 3G Cellular Phones ,\" COOL Chips V Proceedings , Vol. I , pp. 102 -- 111 , April 2002 . T. Tsunoda et al., \"Application Processor for 3G Cellular Phones,\" COOL Chips V Proceedings, Vol. I, pp. 102--111, April 2002.","journal-title":"COOL Chips V Proceedings"},{"key":"e_1_2_1_4_1","first-page":"256","article-title":"A Microprocessor with a 128b CPU, 10 Floating-Point MACs, 4 Floating-Point Dividers, and an MPEG2 Decoder","author":"Kutaragi K.","year":"1999","unstructured":"K. Kutaragi , \" A Microprocessor with a 128b CPU, 10 Floating-Point MACs, 4 Floating-Point Dividers, and an MPEG2 Decoder ,\" ISSCC Dig. Tech. Papers , pp. 256 -- 257 , Feb. 1999 . K. Kutaragi et al., \"A Microprocessor with a 128b CPU, 10 Floating-Point MACs, 4 Floating-Point Dividers, and an MPEG2 Decoder,\" ISSCC Dig. Tech. Papers, pp. 256--257, Feb. 1999.","journal-title":"ISSCC Dig. Tech. Papers"},{"key":"e_1_2_1_5_1","first-page":"414","article-title":"A Dual-Issue Floating-Point Coprocessor with SIMD Architecture and Fast 3D Functions","author":"Rogenmoser R.","year":"2002","unstructured":"R. Rogenmoser , \" A Dual-Issue Floating-Point Coprocessor with SIMD Architecture and Fast 3D Functions ,\" ISSCC Dig. Tech. Papers , pp. 414 -- 415 , Feb. 2002 . R. Rogenmoser et al., \"A Dual-Issue Floating-Point Coprocessor with SIMD Architecture and Fast 3D Functions,\" ISSCC Dig. Tech. Papers, pp. 414--415, Feb. 2002.","journal-title":"ISSCC Dig. Tech. Papers"},{"key":"e_1_2_1_6_1","first-page":"165","volume-title":"HOT Chips IX Symposium Record","author":"Arakawa F.","year":"1997","unstructured":"F. Arakawa RISC Multimedia Microprocessor\" HOT Chips IX Symposium Record , pp. 165 -- 176 , Aug. 1997 . F. Arakawa et al., \"SH4 RISC Multimedia Microprocessor\" HOT Chips IX Symposium Record, pp. 165--176, Aug. 1997."},{"key":"e_1_2_1_7_1","first-page":"288","article-title":"A 200MHz 1.2W 1.4GFLOPS microprocessor with graphic operation unit","author":"Nishii O.","year":"1998","unstructured":"O. Nishii , \" A 200MHz 1.2W 1.4GFLOPS microprocessor with graphic operation unit ,\" ISSCC Dig. Tech. Papers , Feb. 1998 , pp. 288 -- 289 , 447. O. Nishii et al., \"A 200MHz 1.2W 1.4GFLOPS microprocessor with graphic operation unit,\" ISSCC Dig. Tech. Papers, Feb. 1998, pp. 288--289, 447.","journal-title":"ISSCC Dig. Tech. Papers"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.671400"},{"key":"e_1_2_1_9_1","first-page":"334","article-title":"An Embedded Processor Core for Consumer Appliances with 2.8GFLOPS and 36M Polygons\/s FPU","author":"Arakawa F.","year":"2004","unstructured":"F. Arakawa , \" An Embedded Processor Core for Consumer Appliances with 2.8GFLOPS and 36M Polygons\/s FPU ,\" ISSCC Dig. Tech. Papers , pp. 334 -- 335 , 531, Feb. 2004 . F. Arakawa et al., \"An Embedded Processor Core for Consumer Appliances with 2.8GFLOPS and 36M Polygons\/s FPU,\" ISSCC Dig. Tech. Papers, pp. 334--335, 531, Feb. 2004.","journal-title":"ISSCC Dig. Tech. Papers"},{"key":"e_1_2_1_10_1","first-page":"336","article-title":"A Resume-Standby Application Processor for 3G Cellular Phones","author":"Kamei T.","year":"2004","unstructured":"T. Kamei , \" A Resume-Standby Application Processor for 3G Cellular Phones ,\" ISSCC Dig. Tech. Papers , pp. 336 -- 337 , 531, Feb. 2004 . T. Kamei et al., \"A Resume-Standby Application Processor for 3G Cellular Phones,\" ISSCC Dig. Tech. Papers, pp. 336--337, 531, Feb. 2004.","journal-title":"ISSCC Dig. Tech. Papers"},{"key":"e_1_2_1_11_1","volume-title":"USA","author":"Yoshioka S.","year":"2003","unstructured":"S. Yoshioka and T. Hattori , \" SH-X 4500MIPS\/W 2 2-Way Superscalar CPU Core and its SoC Products,\" Microprocessor Forum 2003 Conference Program, Session 4: Low-Power Processors, San Jose , USA , Oct. 2003 . S. Yoshioka and T. Hattori, \"SH-X 4500MIPS\/W 2 2-Way Superscalar CPU Core and its SoC Products,\" Microprocessor Forum 2003 Conference Program, Session 4: Low-Power Processors, San Jose, USA, Oct. 2003."},{"key":"e_1_2_1_12_1","first-page":"168","volume-title":"Dig. Symp. VLSI Circuits","author":"Kanno Y.","year":"2002","unstructured":"Y. Kanno O Architecture for 0.13 &mu;m Wide-Voltage-Range System-on-a-Package (SOP) Designs,\" Dig. Symp. VLSI Circuits , pp. 168 -- 169 , 2002 . Y. Kanno et al., \"&mu;I\/O Architecture for 0.13 &mu;m Wide-Voltage-Range System-on-a-Package (SOP) Designs,\" Dig. Symp. VLSI Circuits, pp. 168--169, 2002."},{"key":"e_1_2_1_13_1","first-page":"494","article-title":"A 300MHz 25 &mu;A\/Mb Leakage On-Chip SRAM Module Featuring Process-Variation Immunity and Low-Leakage-Active Mode for Mobile-Phone Application Processor","author":"Yamaoka M.","year":"2004","unstructured":"M. Yamaoka , \" A 300MHz 25 &mu;A\/Mb Leakage On-Chip SRAM Module Featuring Process-Variation Immunity and Low-Leakage-Active Mode for Mobile-Phone Application Processor \" ISSCC Dig. Tech. Papers , pp. 494 -- 495 , 542, Feb. 2004 . M. Yamaoka et al., \"A 300MHz 25 &mu;A\/Mb Leakage On-Chip SRAM Module Featuring Process-Variation Immunity and Low-Leakage-Active Mode for Mobile-Phone Application Processor\" ISSCC Dig. Tech. Papers, pp. 494--495, 542, Feb. 2004.","journal-title":"ISSCC Dig. Tech. Papers"}],"container-title":["ACM SIGARCH Computer Architecture News"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1101868.1101875","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1101868.1101875","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T16:08:01Z","timestamp":1750262881000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1101868.1101875"}},"subtitle":["an embedded processor core for consumer appliances"],"short-title":[],"issued":{"date-parts":[[2004,9,29]]},"references-count":13,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2005,6]]}},"alternative-id":["10.1145\/1101868.1101875"],"URL":"https:\/\/doi.org\/10.1145\/1101868.1101875","relation":{"is-identical-to":[{"id-type":"doi","id":"10.1145\/1152922.1101875","asserted-by":"subject"}]},"ISSN":["0163-5964"],"issn-type":[{"type":"print","value":"0163-5964"}],"subject":[],"published":{"date-parts":[[2004,9,29]]},"assertion":[{"value":"2004-09-29","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}