{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T21:29:18Z","timestamp":1762032558476,"version":"3.41.0"},"reference-count":30,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2004,9,29]],"date-time":"2004-09-29T00:00:00Z","timestamp":1096416000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGARCH Comput. Archit. News"],"published-print":{"date-parts":[[2005,6]]},"abstract":"<jats:p>In our prior work we explored a cache organization providing architectural support for distinguishing between memory references that exhibit spatial and temporal locality and mapping them to separate caches.That work showed that using separate (data) caches for indexed or stream data and scalar data items could lead to substantial improvements in terms of cache misses. In addition, such a separation allowed for the design of caches that could be tailored to meet the properties exhibited by different data items.In this paper, we investigate the interaction between three established methods: split cache, victim cache and stream buffer. Since significant amounts of compulsory and conflict misses are avoided, the size of each cache (i.e., array and scalar), as well as the combined cache capacity can be reduced. Our results show that on average 55% reduction in miss rates over the base configuration.<\/jats:p>","DOI":"10.1145\/1101868.1101876","type":"journal-article","created":{"date-parts":[[2006,2,6]],"date-time":"2006-02-06T18:14:10Z","timestamp":1139249650000},"page":"41-48","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["Improving data cache performance with integrated use of split caches, victim cache and stream buffers"],"prefix":"10.1145","volume":"33","author":[{"given":"Afrin","family":"Naz","sequence":"first","affiliation":[{"name":"The University of North Texas, Denton, Texas"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mehran","family":"Rezaei","sequence":"additional","affiliation":[{"name":"The University of North Texas, Denton, Texas"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Krishna","family":"Kavi","sequence":"additional","affiliation":[{"name":"The University of North Texas, Denton, Texas"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Philip","family":"Sweany","sequence":"additional","affiliation":[{"name":"The University of North Texas, Denton, Texas"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2004,9,29]]},"reference":[{"key":"e_1_2_1_1_1","first-page":"157","volume-title":"Winnipeg","author":"Naz A.","year":"2004","unstructured":"A. Naz , K. M. Kavi , P. H. Sweany and M. Rezaei . \" A study of separate array and scalar caches\" Proceedings of the 18th International Symposium on High Performance Computing Systems and Applications (HPCS 2004) , Winnipeg , Manitoba, Canada , May 16-19, 2004 , pp 157 -- 164 ]] A. Naz, K. M. Kavi, P. H. Sweany and M. Rezaei. \"A study of separate array and scalar caches\" Proceedings of the 18th International Symposium on High Performance Computing Systems and Applications (HPCS 2004), Winnipeg, Manitoba, Canada, May 16-19, 2004, pp 157--164]]"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/356887.356892"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/125826.125932"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/264107.264213"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.5555\/266800.266806"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/325164.325162"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/165123.165153"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/CMPCON.1994.282903"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/224538.224622"},{"key":"e_1_2_1_10_1","volume-title":"Mar.","author":"Milutinovic V.","year":"1996","unstructured":"V. Milutinovic , M. Tomasevic , B. Markovic , and M. Tremblay , \" The Split Temporal\/Spatial Cache: Initial Performance Analysis,\" SClzzL-5 , Mar. 1996 .]] V. Milutinovic, M. Tomasevic, B. Markovic, and M. Tremblay, \"The Split Temporal\/Spatial Cache: Initial Performance Analysis,\" SClzzL-5, Mar. 1996.]]"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.1996.537156"},{"key":"e_1_2_1_12_1","first-page":"3","volume":"97","author":"Sanchez F. J.","unstructured":"F. J. Sanchez , A. Gonzalez , and M. Valero , \"Software Management of Selective and Dual Data Caches\", IEEE TCCA NEWSLETTERS, March 97 , pp. 3 -- 10 .]] F. J. Sanchez, A. Gonzalez, and M. Valero, \"Software Management of Selective and Dual Data Caches\", IEEE TCCA NEWSLETTERS, March 97, pp. 3--10.]]","journal-title":"IEEE TCCA NEWSLETTERS, March"},{"key":"e_1_2_1_13_1","first-page":"11","volume":"97","author":"Tomasko M.","unstructured":"M. Tomasko , S. Hadjiyiannis , and W. A. Najjar , \"Experimental Evaluation of Array Caches\", IEEE TCCA Newslatters, March 97 , pp. 11 -- 16 .]] M. Tomasko, S. Hadjiyiannis, and W. A. Najjar, \"Experimental Evaluation of Array Caches\", IEEE TCCA Newslatters, March 97, pp. 11--16.]]","journal-title":"IEEE TCCA Newslatters, March"},{"key":"e_1_2_1_14_1","volume-title":"Newsletter of Technical Committee on Computer Architecture, IEEE Computer Society","author":"Milutinovic V.","year":"1999","unstructured":"V. Milutinovic , M. Prvulovic , D. Marinov , Z. Dimitrijevic , \" The Split Spatial\/ Non-Spatial Cache: A Performance and Complexity Evaluation\" , in Newsletter of Technical Committee on Computer Architecture, IEEE Computer Society , July 1999 .]] V. Milutinovic, M. Prvulovic, D. Marinov, Z. Dimitrijevic, \"The Split Spatial\/Non-Spatial Cache:A Performance and Complexity Evaluation\", in Newsletter of Technical Committee on Computer Architecture, IEEE Computer Society, July 1999.]]"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1016\/S1383-7621(00)00035-7"},{"key":"e_1_2_1_16_1","volume-title":"June","author":"Lee J. H.","year":"2000","unstructured":"J. H. Lee , G. H. Park , K. W. Lee , T. D. Han , and S. D. Kim , \" A Power Efficient Cache Structure for Embedded Processors Based on the Dual Cache Structure,\" In proceedings of the ACM LCTES'2000 , June 2000 .]] J. H. Lee, G. H. Park, K. W. Lee, T. D. Han, and S. D. Kim, \"A Power Efficient Cache Structure for Embedded Processors Based on the Dual Cache Structure,\" In proceedings of the ACM LCTES'2000, June 2000.]]"},{"key":"e_1_2_1_17_1","unstructured":"Intel StrongARM SA-1110 Microprocessor Brief Datasheet April 2000.]]  Intel StrongARM SA-1110 Microprocessor Brief Datasheet April 2000.]]"},{"key":"e_1_2_1_18_1","first-page":"131","volume-title":"MA","author":"Unsal O. S.","year":"2002","unstructured":"O. S. Unsal , I. Koren , C. M. Krishna , C. A. Moritz , \" The Minimax Cache : An Energy-Efficient Framework for Media Processors,\" 8th International Symposium on High-Performance Computer Architecture, HPCA8, Cambridge , MA , February 2002 , pp. 131 -- 140 .]] O. S. Unsal, I. Koren, C. M. Krishna, C. A. Moritz, \"The Minimax Cache: An Energy-Efficient Framework for Media Processors,\" 8th International Symposium on High-Performance Computer Architecture, HPCA8, Cambridge, MA, February 2002, pp. 131--140.]]"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339685"},{"key":"e_1_2_1_20_1","volume-title":"IEEE Volta International Workshop on Low Power Design","author":"Albera G.","year":"1999","unstructured":"G. Albera , R. I. Bahar , \"Power\/Performance Advantages of a Victim Buffer in High-Performance Processors \", IEEE Volta International Workshop on Low Power Design , Como, Italy , March 1999 .]] G. Albera, R. I. Bahar, \"Power\/Performance Advantages of a Victim Buffer in High-Performance Processors\", IEEE Volta International Workshop on Low Power Design, Como, Italy, March 1999.]]"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/309758.309781"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/263580.263651"},{"volume-title":"Proceedings of DSD'2002 Dortmund","author":"Hormdee D.","key":"e_1_2_1_23_1","unstructured":"D. Hormdee , J. D. Garside , S. B. Furber , \" An Asynchronous Victim Cache\" , Proceedings of DSD'2002 Dortmund , September 2002]] D. Hormdee, J. D. Garside, S. B. Furber, \"An Asynchronous Victim Cache\", Proceedings of DSD'2002 Dortmund, September 2002]]"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.5555\/968878.968997"},{"key":"e_1_2_1_25_1","volume-title":"Proceedings of the 27th Hawaii International Conference on System Sciences","author":"Stiliadis Dimitrios","year":"1994","unstructured":"Dimitrios Stiliadis . \" Selective victim caching : A method to improve the performance of direct-mapped caches \", In Proceedings of the 27th Hawaii International Conference on System Sciences , Los Alamitos, California , 1994 . IEEE, Computer Society Press.]] Dimitrios Stiliadis. \"Selective victim caching: A method to improve the performance of direct-mapped caches\", In Proceedings of the 27th Hawaii International Conference on System Sciences, Los Alamitos, California, 1994. IEEE, Computer Society Press.]]"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.689677"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/191995.192014"},{"key":"e_1_2_1_28_1","first-page":"423","volume-title":"Computer Architecture A Quantitative Approach","author":"Hennessy J. L.","year":"2003","unstructured":"J. L. Hennessy and D. A. Patterson , Computer Architecture A Quantitative Approach , Morgan Kaufmann Publishers , Third Edition 2003 , pp 423 -- 430 .]] J. L. Hennessy and D. A. Patterson, Computer Architecture A Quantitative Approach, Morgan Kaufmann Publishers, Third Edition 2003, pp 423--430.]]"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.869367"},{"key":"e_1_2_1_30_1","volume-title":"TN-44","author":"Eustance A.","year":"1994","unstructured":"A. Eustance and A. Srivastava , \" ATOM: A flexible interface for building high performance program analysis tools\", Western Research Laboratory , TN-44 , 1994 .]] A. Eustance and A. Srivastava, \"ATOM: A flexible interface for building high performance program analysis tools\", Western Research Laboratory, TN-44, 1994.]]"}],"container-title":["ACM SIGARCH Computer Architecture News"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1101868.1101876","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1101868.1101876","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T16:08:01Z","timestamp":1750262881000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1101868.1101876"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2004,9,29]]},"references-count":30,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2005,6]]}},"alternative-id":["10.1145\/1101868.1101876"],"URL":"https:\/\/doi.org\/10.1145\/1101868.1101876","relation":{"is-identical-to":[{"id-type":"doi","id":"10.1145\/1152922.1101876","asserted-by":"subject"}]},"ISSN":["0163-5964"],"issn-type":[{"type":"print","value":"0163-5964"}],"subject":[],"published":{"date-parts":[[2004,9,29]]},"assertion":[{"value":"2004-09-29","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}