{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:08:52Z","timestamp":1763467732232,"version":"3.41.0"},"reference-count":19,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2005,11,1]],"date-time":"2005-11-01T00:00:00Z","timestamp":1130803200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGARCH Comput. Archit. News"],"published-print":{"date-parts":[[2005,11]]},"abstract":"<jats:p>With the advent of dual-core chips in the marketplace, small-scale CMP (chip multiprocessor) architectures are becoming commonplace. We expect a continuing trend of increasing the number of cores on a die to maximize the performance\/power efficiency of a single chip. We believe an era of large-scale CMPs (LCMPs) with several tens to hundreds of cores is on the way, but as of now architects have little understanding of how best to build a cache hierarchy given such a large number of cores\/threads to support. With this in mind, our initial goals are to prune the cache design space for LCMPs by characterizing basic server workload behavior in such an environment.In this paper, we describe the range of methodologies that we are developing to overcome the challenges of exploring the cache design space for LCMP platforms. We then focus on employing a trace-driven approach to characterizing one key server workload (OLTP) in both a homogeneous and a heterogeneous workload environment. We study the effect of increasing threads (from 1 to 128) on a three-level cache hierarchy with emphasis on second and third level caches. We study the effect of varying sizes at these cache levels and show the effects of threads contending for cache space, the effects of prefetching instruction addresses, and the effects of inclusion. We make initial observations and conclusions about the factors on which LCMP cache hierarchy design decisions should be based and discuss future work.<\/jats:p>","DOI":"10.1145\/1105734.1105739","type":"journal-article","created":{"date-parts":[[2006,2,6]],"date-time":"2006-02-06T18:14:10Z","timestamp":1139249650000},"page":"24-33","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":50,"title":["Exploring the cache design space for large scale CMPs"],"prefix":"10.1145","volume":"33","author":[{"given":"Lisa","family":"Hsu","sequence":"first","affiliation":[{"name":"University of Michigan, Ann Arbor"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ravi","family":"Iyer","sequence":"additional","affiliation":[{"name":"Systems Technology Lab, Intel Corporation"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Srihari","family":"Makineni","sequence":"additional","affiliation":[{"name":"Systems Technology Lab, Intel Corporation"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Steve","family":"Reinhardt","sequence":"additional","affiliation":[{"name":"University of Michigan, Ann Arbor"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Donald","family":"Newell","sequence":"additional","affiliation":[{"name":"Systems Technology Lab, Intel Corporation"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2005,11]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"\"Azul Compute Appliance \" Azul Systems can be found http:\/\/www.azulsystems.com\/products\/cpools_cappliance.html  \"Azul Compute Appliance \" Azul Systems can be found http:\/\/www.azulsystems.com\/products\/cpools_cappliance.html"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/945445.945462"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.612253"},{"key":"e_1_2_1_4_1","unstructured":"Intel Corporation. \"Intel Dual-Core Processors -- The First in the Multi-core Revolution \" http:\/\/www.intel.com\/technology\/computing\/dual-core\/  Intel Corporation. \"Intel Dual-Core Processors -- The First in the Multi-core Revolution \" http:\/\/www.intel.com\/technology\/computing\/dual-core\/"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1006209.1006246"},{"key":"e_1_2_1_6_1","volume-title":"11th IEEE\/ACM Symposium on Modeling, Analysis and Simulation of Computer and Telecom Systems","author":"Iyer R.","year":"2003","unstructured":"R. Iyer , \"On Modeling and Analyzing Cache Hierarchies using CASPER\" , 11th IEEE\/ACM Symposium on Modeling, Analysis and Simulation of Computer and Telecom Systems , Oct 2003 . R. Iyer, \"On Modeling and Analyzing Cache Hierarchies using CASPER\", 11th IEEE\/ACM Symposium on Modeling, Analysis and Simulation of Computer and Telecom Systems, Oct 2003."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.35"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.34"},{"key":"e_1_2_1_9_1","first-page":"638","article-title":"Implementation of HW$im - A Real-Time Configurable Cache Simulator","volume":"2003","author":"Lu S-L.","unstructured":"S-L. Lu and K. Lai , \" Implementation of HW$im - A Real-Time Configurable Cache Simulator ,\" FPL 2003 : 638 -- 647 S-L. Lu and K. Lai, \"Implementation of HW$im - A Real-Time Configurable Cache Simulator,\" FPL 2003: 638--647","journal-title":"FPL"},{"issue":"1","key":"e_1_2_1_10_1","article-title":"Hyper-Threading Technology Architecture and Microarchitecture","volume":"3","author":"Marr D.","year":"2002","unstructured":"D. Marr , F. Binns , , \" Hyper-Threading Technology Architecture and Microarchitecture ,\" Intel Technology Journal , Vol 3 , Issue 1 , Feb 2002 , can be found at ftp:\/\/download.intel.com\/technology\/itj\/2002\/volume06issue01\/vol6iss1_hyper_threading_technology.pdf D. Marr, F. Binns, et al., \"Hyper-Threading Technology Architecture and Microarchitecture,\" Intel Technology Journal, Vol 3, Issue 1, Feb 2002, can be found at ftp:\/\/download.intel.com\/technology\/itj\/2002\/volume06issue01\/vol6iss1_hyper_threading_technology.pdf","journal-title":"Intel Technology Journal"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/356989.356993"},{"key":"e_1_2_1_12_1","unstructured":"SPECjAppserver2004 User's Guide http:\/\/www.spec.org\/jAppServer2004\/docs\/UserGuide.html  SPECjAppserver2004 User's Guide http:\/\/www.spec.org\/jAppServer2004\/docs\/UserGuide.html"},{"key":"e_1_2_1_13_1","unstructured":"Sap America Inc. \"SAP Standard Benchmarks \" http:\/\/www.sap.com\/solutions\/benchmark\/index.epx  Sap America Inc. \"SAP Standard Benchmarks \" http:\/\/www.sap.com\/solutions\/benchmark\/index.epx"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.10"},{"key":"e_1_2_1_15_1","unstructured":"\"TPC-C Design Document\" available online on the TPC website at www.tpc.org\/tpcc\/  \"TPC-C Design Document\" available online on the TPC website at www.tpc.org\/tpcc\/"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/223982.224449"},{"key":"e_1_2_1_17_1","first-page":"Q4","article-title":"SoftSDV: A Presilicon Software Development Environment for the IA-64 Architecture","author":"Uhlig R.","year":"1999","unstructured":"R. Uhlig , R. Fishtein , et. al. , \" SoftSDV: A Presilicon Software Development Environment for the IA-64 Architecture . Intel Technology Journal. Q4 , 1999 . (http:\/\/www.intel.com\/technology\/itjf) R. Uhlig, R. Fishtein, et. al., \"SoftSDV: A Presilicon Software Development Environment for the IA-64 Architecture. Intel Technology Journal. Q4, 1999. (http:\/\/www.intel.com\/technology\/itjf)","journal-title":"Intel Technology Journal."},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2005.163"},{"key":"e_1_2_1_19_1","volume-title":"Feb.","author":"Zhao L.","year":"2004","unstructured":"L. Zhao , R. Illikkal , S. Makineni and L. Bhuyan , \" TCP\/IP Cache Characterization in Commercial Server Workloads,\" 7th Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-7), held along with HPCA-10 , Feb. 2004 . L. Zhao, R. Illikkal, S. Makineni and L. Bhuyan, \"TCP\/IP Cache Characterization in Commercial Server Workloads,\" 7th Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-7), held along with HPCA-10, Feb. 2004."}],"container-title":["ACM SIGARCH Computer Architecture News"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1105734.1105739","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1105734.1105739","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T16:08:03Z","timestamp":1750262883000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1105734.1105739"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005,11]]},"references-count":19,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2005,11]]}},"alternative-id":["10.1145\/1105734.1105739"],"URL":"https:\/\/doi.org\/10.1145\/1105734.1105739","relation":{},"ISSN":["0163-5964"],"issn-type":[{"type":"print","value":"0163-5964"}],"subject":[],"published":{"date-parts":[[2005,11]]},"assertion":[{"value":"2005-11-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}