{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:41:41Z","timestamp":1750308101817,"version":"3.41.0"},"reference-count":39,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2005,11,1]],"date-time":"2005-11-01T00:00:00Z","timestamp":1130803200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGARCH Comput. Archit. News"],"published-print":{"date-parts":[[2005,11]]},"abstract":"<jats:p>We describe a hybrid hardware emulation environment: the Flexible Architecture for Simulation and Testing (FAST). FAST integrates field-programmable gate arrays (FPGAs), microprocessors, and memory to enable rapid prototyping of chip multiprocessors, multithreaded architectures, or other novel computer architectures and chip-level memory systems. FAST combines configurable and fixed-function hardware and software to facilitate rapid prototyping by utilizing components optimized for their particular tasks: FPGAs for interconnect and glue logic; processors for rapid program execution; and SRAMs for fast memory. Unlike software simulators, FAST can simulate complex designs at multi-megahertz speeds regardless of the simulation detail. We illustrate FAST's utility by describing mappings of both a small-scale CMP with speculation support and a large-scale CMP connected using a network. We then show performance results from a very simple, decoupled 4-way CMP executing small test programs.<\/jats:p>","DOI":"10.1145\/1105734.1105740","type":"journal-article","created":{"date-parts":[[2006,2,6]],"date-time":"2006-02-06T18:14:10Z","timestamp":1139249650000},"page":"34-43","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["A chip prototyping substrate"],"prefix":"10.1145","volume":"33","author":[{"given":"John D.","family":"Davis","sequence":"first","affiliation":[{"name":"Stanford University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stephen E.","family":"Richardson","sequence":"additional","affiliation":[{"name":"Stanford University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Charis","family":"Charitsis","sequence":"additional","affiliation":[{"name":"Stanford University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kunle","family":"Olukotun","sequence":"additional","affiliation":[{"name":"Stanford University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2005,11]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.982917"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.347997"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.997876"},{"key":"e_1_2_1_4_1","volume-title":"Parallel Computer Architecure A Hardware\/Software Approach","author":"Culler D.","year":"1999","unstructured":"D. Culler and J. P. Singh , Parallel Computer Architecure A Hardware\/Software Approach , Morgan Kaufmann Publishers, Inc. San Francisco, CA , 1999 D. Culler and J. P. Singh, Parallel Computer Architecure A Hardware\/Software Approach, Morgan Kaufmann Publishers, Inc. San Francisco, CA, 1999"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2005.42"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/54.706042"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.982918"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.848474"},{"key":"e_1_2_1_9_1","first-page":"24","article-title":"Garp: A MIPS Processor with a Reconfigurable Coprocessor","author":"Hauser J. R.","year":"1997","unstructured":"J. R. Hauser and J. Wawrzynek , \" Garp: A MIPS Processor with a Reconfigurable Coprocessor ,\" IEEE Workshop on FPGAs for Custom Computing Machines , pp. 24 -- 33 , 1997 J. R. Hauser and J. Wawrzynek, \"Garp: A MIPS Processor with a Reconfigurable Coprocessor,\" IEEE Workshop on FPGAs for Custom Computing Machines, pp. 24--33, 1997","journal-title":"IEEE Workshop on FPGAs for Custom Computing Machines"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.982915"},{"key":"e_1_2_1_11_1","first-page":"199","article-title":"Exploring the Design Space of Future CMPs","author":"Huh J.","year":"2001","unstructured":"J. Huh , , \" Exploring the Design Space of Future CMPs ,\" PACT , pp. 199 -- 210 , Sept. 2001 . J. Huh, et al., \"Exploring the Design Space of Future CMPs,\" PACT, pp. 199--210, Sept. 2001.","journal-title":"PACT"},{"key":"e_1_2_1_12_1","unstructured":"R. Kalla B. Sinharoy J. Tendler \"Simultaneouos Multi-threading Implementation in POWER5 \" Hot Chips 15 Aug 2003  R. Kalla B. Sinharoy J. Tendler \"Simultaneouos Multi-threading Implementation in POWER5 \" Hot Chips 15 Aug 2003"},{"key":"e_1_2_1_13_1","volume-title":"A Power-efficient Chip Multi-Threaded (CMT) UltraSPARC\u00ae Processor,\" Hot Chips","author":"Kapil S.","year":"2003","unstructured":"S. Kapil , \"Gemini : A Power-efficient Chip Multi-Threaded (CMT) UltraSPARC\u00ae Processor,\" Hot Chips 15, Aug 2003 S. Kapil, \"Gemini: A Power-efficient Chip Multi-Threaded (CMT) UltraSPARC\u00ae Processor,\" Hot Chips 15, Aug 2003"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1196115"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.795218"},{"key":"e_1_2_1_16_1","volume-title":"The 31st International Symposium on Computer Architecture (ISCA-31)","author":"Kumar R.","year":"2004","unstructured":"R. Kumar , D. Tullsen , ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance ,\" The 31st International Symposium on Computer Architecture (ISCA-31) , June 2004 . R. Kumar, D. Tullsen, et al., \"Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance,\" The 31st International Symposium on Computer Architecture (ISCA-31), June 2004."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339673"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.612245"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/244804.244807"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859667"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/223982.224451"},{"key":"e_1_2_1_24_1","volume-title":"February 2--4","author":"Steffan J.","year":"1998","unstructured":"J. Steffan and T. Mowry , \" The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization,\" Proceedings of the Fourth International Symposium on High-Performance Computer Architecture (HPCA-4) , February 2--4 , 1998 . J. Steffan and T. Mowry, \"The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization,\" Proceedings of the Fourth International Symposium on High-Performance Computer Architecture (HPCA-4), February 2--4, 1998."},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.612254"},{"key":"e_1_2_1_26_1","volume-title":"Digital Western Research Laboratory","author":"Wall D. W.","year":"1993","unstructured":"D. W. Wall , \" Limits of Instruction-Level Parallelism ,\" WRL Research Report 93\/6 , Digital Western Research Laboratory , Palo Alto, CA , 1993 D. W. Wall, \"Limits of Instruction-Level Parallelism,\" WRL Research Report 93\/6, Digital Western Research Laboratory, Palo Alto, CA, 1993"},{"key":"e_1_2_1_27_1","volume-title":"Integrated Device Technology","author":"Guide Designer's","year":"1990","unstructured":"R3000\/R3001 Designer's Guide , Integrated Device Technology , Inc ., 1990 R3000\/R3001 Designer's Guide, Integrated Device Technology, Inc., 1990"},{"key":"e_1_2_1_28_1","unstructured":"Altera Development Kits http:\/\/www.altera.com\/products\/devkits\/kit-dev_platforms.jsp  Altera Development Kits http:\/\/www.altera.com\/products\/devkits\/kit-dev_platforms.jsp"},{"key":"e_1_2_1_29_1","unstructured":"128\n    Megabit (16 M x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with Versatile I\/O Control Data Sheet http:\/\/www.amd.com\/us-en\/assets\/content_type\/white_papers_and_tech_docs\/24961.pdf  128 Megabit (16 M x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with Versatile I\/O Control Data Sheet http:\/\/www.amd.com\/us-en\/assets\/content_type\/white_papers_and_tech_docs\/24961.pdf"},{"key":"e_1_2_1_30_1","unstructured":"Artesyn Technologies' Processor Blades and Processor subsystems http:\/\/www.artesyncp.com\/products\/index.html  Artesyn Technologies' Processor Blades and Processor subsystems http:\/\/www.artesyncp.com\/products\/index.html"},{"key":"e_1_2_1_31_1","unstructured":"PMON5 http:\/\/www.carmel.com\/pmon\/index.html  PMON5 http:\/\/www.carmel.com\/pmon\/index.html"},{"key":"e_1_2_1_32_1","unstructured":"GNU GDB http:\/\/www.gnu.org\/directory\/GNU\/gdb.html GNU GDB http:\/\/www.gnu.org\/directory\/GNU\/gdb.html"},{"key":"e_1_2_1_33_1","unstructured":"1Mb X 36 S\/DCD Sync Burst SRAMs http:\/\/www.gsitechnology.com\/8324183672.pdf  1Mb X 36 S\/DCD Sync Burst SRAMs http:\/\/www.gsitechnology.com\/8324183672.pdf"},{"key":"e_1_2_1_34_1","unstructured":"High-Speed 3.3V 64K x 36 Asynchronous Dual-Port SRAM http:\/\/www.idt.com\/products\/pages\/Multi-Ports-70V658.html  High-Speed 3.3V 64K x 36 Asynchronous Dual-Port SRAM http:\/\/www.idt.com\/products\/pages\/Multi-Ports-70V658.html"},{"key":"e_1_2_1_35_1","unstructured":"Mentor Emulation Products http:\/\/www.mentor.com\/emulation  Mentor Emulation Products http:\/\/www.mentor.com\/emulation"},{"key":"e_1_2_1_36_1","unstructured":"RCM3200 RabbitCore User's Manual http:\/\/www.rabbitsemiconductor.com\/products\/rcm3200\/docs.shtml  RCM3200 RabbitCore User's Manual http:\/\/www.rabbitsemiconductor.com\/products\/rcm3200\/docs.shtml"},{"key":"e_1_2_1_37_1","unstructured":"Fujitsu Motorola STMicroelectronics Synopsys CoWare and Cadence System-C Version 2.0 User Guide 2002. Available at http:\/\/www.systemc.org  Fujitsu Motorola STMicroelectronics Synopsys CoWare and Cadence System-C Version 2.0 User Guide 2002. Available at http:\/\/www.systemc.org"},{"key":"e_1_2_1_38_1","unstructured":"Xtensa Product Brief http:\/\/www.tensilica.com\/Xtensa_PB_1003.pdf  Xtensa Product Brief http:\/\/www.tensilica.com\/Xtensa_PB_1003.pdf"},{"key":"e_1_2_1_39_1","unstructured":"FPGA Development Boards http:\/\/www.xilinx.com\/  FPGA Development Boards http:\/\/www.xilinx.com\/"},{"key":"e_1_2_1_40_1","unstructured":"Xilinx Datasheets http:\/\/www.xilinx.com\/xlnx\/xweb\/xil_publications_index.jsp  Xilinx Datasheets http:\/\/www.xilinx.com\/xlnx\/xweb\/xil_publications_index.jsp"}],"container-title":["ACM SIGARCH Computer Architecture News"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1105734.1105740","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1105734.1105740","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T16:08:03Z","timestamp":1750262883000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1105734.1105740"}},"subtitle":["the flexible architecture for simulation and testing (FAST)"],"short-title":[],"issued":{"date-parts":[[2005,11]]},"references-count":39,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2005,11]]}},"alternative-id":["10.1145\/1105734.1105740"],"URL":"https:\/\/doi.org\/10.1145\/1105734.1105740","relation":{},"ISSN":["0163-5964"],"issn-type":[{"type":"print","value":"0163-5964"}],"subject":[],"published":{"date-parts":[[2005,11]]},"assertion":[{"value":"2005-11-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}