{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:41:42Z","timestamp":1750308102485,"version":"3.41.0"},"reference-count":25,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2005,11,1]],"date-time":"2005-11-01T00:00:00Z","timestamp":1130803200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGARCH Comput. Archit. News"],"published-print":{"date-parts":[[2005,11]]},"abstract":"<jats:p>Microprocessor speeds have been improving much faster than memory speeds, resulting in the CPU spending a larger and larger amount of time waiting for data. Processor designers have employed several ways to improve memory performance, including hierarchical caching, prefetching, and faster memory chips. Yet, memory accesses still represent a major performance bottleneck and much remains to be done to tolerate the increasing memory latencies. Load-value prediction has been shown to effectively hide some of this latency. However, the hardware required to achieve good performance is substantial, making load-value prediction unappealing in light of increasing power constraints. In this paper, we present a novel predictor that significantly increases CPU performance while at the same time decreasing the energy consumption of the entire processor relative to a baseline with a well-performing hybrid load-value predictor.<\/jats:p>","DOI":"10.1145\/1105734.1105751","type":"journal-article","created":{"date-parts":[[2006,2,6]],"date-time":"2006-02-06T18:14:10Z","timestamp":1139249650000},"page":"121-127","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Improving memory system performance with energy-efficient value speculation"],"prefix":"10.1145","volume":"33","author":[{"given":"Nana B.","family":"Sam","sequence":"first","affiliation":[{"name":"Cornell University, Ithaca, NY"}]},{"given":"Martin","family":"Burtscher","sequence":"additional","affiliation":[{"name":"Cornell University, Ithaca, NY"}]}],"member":"320","published-online":{"date-parts":[[2005,11]]},"reference":[{"key":"e_1_2_1_1_1","first-page":"71","volume-title":"Performance and Energy Impact of Instruction-Level Value Predictor Filtering. First Value-Prediction Workshop","author":"Bhargava R.","year":"2003","unstructured":"R. Bhargava , L. K. John . Performance and Energy Impact of Instruction-Level Value Predictor Filtering. First Value-Prediction Workshop , 2003 , pp. 71 -- 78 . R. Bhargava, L. K. John. Performance and Energy Impact of Instruction-Level Value Predictor Filtering. First Value-Prediction Workshop, 2003, pp. 71--78."},{"key":"e_1_2_1_2_1","first-page":"171","volume-title":"Wattch: A Framework for High-Performance Microprocessors. Seventh International Symposium on High-Performance Computer Architecture","author":"Brooks D.","year":"2001","unstructured":"D. Brooks , V. Tiwari , M. Martonosi . Wattch: A Framework for High-Performance Microprocessors. Seventh International Symposium on High-Performance Computer Architecture , 2001 , pp. 171 -- 182 . D. Brooks, V. Tiwari, M. Martonosi. Wattch: A Framework for High-Performance Microprocessors. Seventh International Symposium on High-Performance Computer Architecture, 2001, pp. 171--182."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/268806.268810"},{"key":"e_1_2_1_4_1","volume-title":"Journal of Instruction-Level Parallelism","author":"Burtscher M.","year":"1999","unstructured":"M. Burtscher , B. G. Zorn . Prediction Outcome History-based Confidence Estimation for Load Value Prediction . Journal of Instruction-Level Parallelism , 1999 . M. Burtscher, B. G. Zorn. Prediction Outcome History-based Confidence Estimation for Load Value Prediction. Journal of Instruction-Level Parallelism, 1999."},{"key":"e_1_2_1_5_1","first-page":"81","volume-title":"Hybridizing and Coalescing Load Value Predictors. International Conference on Computer Design","author":"Burtscher M.","year":"2000","unstructured":"M. Burtscher , B. G. Zorn . Hybridizing and Coalescing Load Value Predictors. International Conference on Computer Design , 2000 , pp. 81 -- 92 . M. Burtscher, B. G. Zorn. Hybridizing and Coalescing Load Value Predictors. International Conference on Computer Design, 2000, pp. 81--92."},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2002.1017696"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/300979.300985"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.5555\/580550.876442"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/277830.277840"},{"key":"e_1_2_1_11_1","first-page":"1227","author":"Gonzalez R.","year":"1996","unstructured":"R. Gonzalez , M. Horowitz. Energy Dissipation in General Purpose Microprocessors. IEEE Journal of Solid-State Circuits , 1996 , pp. 1227 -- 1284 . R. Gonzalez, M. Horowitz. Energy Dissipation in General Purpose Microprocessors. IEEE Journal of Solid-State Circuits, 1996, pp. 1227--1284.","journal-title":"Horowitz. Energy Dissipation in General Purpose Microprocessors. IEEE Journal of Solid-State Circuits"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/237090.237173"},{"key":"e_1_2_1_13_1","first-page":"1","year":"2003","unstructured":"G. H. Loh. Width-Partitioned Load Value Predictors. Journal of Instruction-Level Parallelism , 2003 , pp. 1 -- 23 . G. H. Loh. Width-Partitioned Load Value Predictors. Journal of Instruction-Level Parallelism, 2003, pp. 1--23.","journal-title":"G. H. Loh. Width-Partitioned Load Value Predictors. Journal of Instruction-Level Parallelism"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.5555\/557517.846878"},{"key":"e_1_2_1_15_1","first-page":"1291","author":"Pinuel L.","year":"1999","unstructured":"L. Pinuel , R. A. Moreno , F. Tirado . Implementation of Hybrid Context Based Value Predictors Using Value Sequence Classification. Euro-Par , 1999 , pp. 1291 -- 1295 . L. Pinuel, R. A. Moreno, F. Tirado. Implementation of Hybrid Context Based Value Predictors Using Value Sequence Classification. Euro-Par, 1999, pp. 1291--1295.","journal-title":"Euro-Par"},{"key":"e_1_2_1_16_1","first-page":"127","volume-title":"Predictive Techniques for Aggressive Load Speculation. 31stIEEE\/ACM International Symposium on Microarchitecture","author":"Reinman G.","year":"1998","unstructured":"G. Reinman , B. Calder . Predictive Techniques for Aggressive Load Speculation. 31stIEEE\/ACM International Symposium on Microarchitecture , 1998 , pp. 127 -- 137 . G. Reinman, B. Calder. Predictive Techniques for Aggressive Load Speculation. 31stIEEE\/ACM International Symposium on Microarchitecture, 1998, pp. 127--137."},{"key":"e_1_2_1_17_1","first-page":"148","volume-title":"Efficacy and Performance Impact of Value Prediction. International Conference on Parallel Architectures and Compilation Techniques","author":"Rychlik B.","year":"1998","unstructured":"B. Rychlik , J. Faistl , B. Krug , J. P. Shen . Efficacy and Performance Impact of Value Prediction. International Conference on Parallel Architectures and Compilation Techniques , 1998 , pp. 148 -- 154 . B. Rychlik, J. Faistl, B. Krug, J. P. Shen. Efficacy and Performance Impact of Value Prediction. International Conference on Parallel Architectures and Compilation Techniques, 1998, pp. 148--154."},{"key":"e_1_2_1_18_1","first-page":"32","volume-title":"Exploiting Type Information in Load-Value Predictors. Second Value-Prediction and Value-Based Optimization Workshop","author":"Sam N. B.","year":"2004","unstructured":"N. B. Sam , M. Burtscher . Exploiting Type Information in Load-Value Predictors. Second Value-Prediction and Value-Based Optimization Workshop , 2004 , pp. 32 -- 39 . N. B. Sam, M. Burtscher. Exploiting Type Information in Load-Value Predictors. Second Value-Prediction and Value-Based Optimization Workshop, 2004, pp. 32--39."},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1062261.1062320"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/335231.335250"},{"key":"e_1_2_1_21_1","first-page":"106","volume-title":"Low-Cost Value Prediction Using Frequent Value Locality. Fourth International Symposium on High Performance Computing","author":"Sato T.","year":"2002","unstructured":"T. Sato , I. Arita . Low-Cost Value Prediction Using Frequent Value Locality. Fourth International Symposium on High Performance Computing , 2002 , pp. 106 -- 119 . T. Sato, I. Arita. Low-Cost Value Prediction Using Frequent Value Locality. Fourth International Symposium on High Performance Computing, 2002, pp. 106--119."},{"key":"e_1_2_1_22_1","first-page":"248","volume-title":"The Predictability of Data Values. Thirteenth IEEE\/ACM International Symposium on Microarchitecture","author":"Sazeides Y.","year":"1997","unstructured":"Y. Sazeides , J. E. Smith . The Predictability of Data Values. Thirteenth IEEE\/ACM International Symposium on Microarchitecture , 1997 , pp. 248 -- 258 . Y. Sazeides, J. E. Smith. The Predictability of Data Values. Thirteenth IEEE\/ACM International Symposium on Microarchitecture, 1997, pp. 248--258."},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605403"},{"key":"e_1_2_1_24_1","volume-title":"Power and Area Model. TR 2001\/2. Compaq Western Research Laboratory","author":"Shivakumar P.","year":"2001","unstructured":"P. Shivakumar , N. P. Jouppi . CACTI 3.0 : An Integrated Cache Timing , Power and Area Model. TR 2001\/2. Compaq Western Research Laboratory , 2001 . P. Shivakumar, N. P. Jouppi. CACTI 3.0: An Integrated Cache Timing, Power and Area Model. TR 2001\/2. Compaq Western Research Laboratory, 2001."},{"key":"e_1_2_1_25_1","unstructured":"SPECcpu2000 benchmarks. http:\/\/www.spec.org\/osg\/cpu2000.  SPECcpu2000 benchmarks. http:\/\/www.spec.org\/osg\/cpu2000."},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.5555\/266800.266827"}],"container-title":["ACM SIGARCH Computer Architecture News"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1105734.1105751","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1105734.1105751","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T16:08:03Z","timestamp":1750262883000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1105734.1105751"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005,11]]},"references-count":25,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2005,11]]}},"alternative-id":["10.1145\/1105734.1105751"],"URL":"https:\/\/doi.org\/10.1145\/1105734.1105751","relation":{},"ISSN":["0163-5964"],"issn-type":[{"type":"print","value":"0163-5964"}],"subject":[],"published":{"date-parts":[[2005,11]]},"assertion":[{"value":"2005-11-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}