{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:08:58Z","timestamp":1763467738931,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":24,"publisher":"ACM","license":[{"start":{"date-parts":[[2006,2,22]],"date-time":"2006-02-22T00:00:00Z","timestamp":1140566400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2006,2,22]]},"DOI":"10.1145\/1117201.1117203","type":"proceedings-article","created":{"date-parts":[[2006,5,8]],"date-time":"2006-05-08T21:40:43Z","timestamp":1147124443000},"page":"3-11","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":39,"title":["A 90nm low-power FPGA for battery-powered applications"],"prefix":"10.1145","author":[{"given":"Tim","family":"Tuan","sequence":"first","affiliation":[{"name":"Xilinx Research Labs, San Jose, CA"}]},{"given":"Sean","family":"Kao","sequence":"additional","affiliation":[{"name":"Xilinx Research Labs, San Jose, CA"}]},{"given":"Arif","family":"Rahman","sequence":"additional","affiliation":[{"name":"Xilinx Research Labs, San Jose, CA"}]},{"given":"Satyaki","family":"Das","sequence":"additional","affiliation":[{"name":"Xilinx Research Labs, San Jose, CA"}]},{"given":"Steve","family":"Trimberger","sequence":"additional","affiliation":[{"name":"Xilinx Research Labs, San Jose, CA"}]}],"member":"320","published-online":{"date-parts":[[2006,2,22]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Digital Integrated Circuits: A Design Perspective","author":"Rabaey J.","year":"2003","unstructured":"J. Rabaey ., A. Chandrakasan , B. Nikolic , Digital Integrated Circuits: A Design Perspective , 2 nd Edition, Prentice Hall , 2003 . J. Rabaey., A. Chandrakasan, B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd Edition, Prentice Hall, 2003.","edition":"2"},{"key":"e_1_3_2_1_2_1","unstructured":"Intel Corp. PXA270 Processor Datasheet http:\/\/www.intel.com.  Intel Corp. PXA270 Processor Datasheet http:\/\/www.intel.com."},{"key":"e_1_3_2_1_3_1","unstructured":"Texas Instruments OMAP5910 Dual-Core Processor Data Manual http:\/\/www.ti.com.  Texas Instruments OMAP5910 Dual-Core Processor Data Manual http:\/\/www.ti.com."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1117\/12.512542"},{"key":"e_1_3_2_1_5_1","volume-title":"Proceedings of ISSCC","author":"S. Mutoh","year":"1996","unstructured":"S. Mutoh et al, \" A 1V Multi-Threshold Voltage CMOS DSP with an Efficient Power Management Technique for Mobile Phone Application \", Proceedings of ISSCC , 1996 . S. Mutoh et al, \"A 1V Multi-Threshold Voltage CMOS DSP with an Efficient Power Management Technique for Mobile Phone Application\", Proceedings of ISSCC, 1996."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/566408.566413"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065653"},{"key":"e_1_3_2_1_8_1","volume-title":"Proc. of Int'l Solid-State Circuits Conference","author":"Royannez P.","year":"2005","unstructured":"P. Royannez , \"90nm Low-Leakage SoC Design Techniques for Wireless Applications\" , Proc. of Int'l Solid-State Circuits Conference , 2005 . P. Royannez, \"90nm Low-Leakage SoC Design Techniques for Wireless Applications\", Proc. of Int'l Solid-State Circuits Conference, 2005."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.5555\/996070.1009965"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/968280.968289"},{"key":"e_1_3_2_1_11_1","volume-title":"Proc of Int'l Conference on Field-Programmable Technology","author":"Anderson J.","year":"2002","unstructured":"J. Anderson , F. Najm , \" Power-Aware Technology Mapping for LUT-Based FPGAs\" , Proc of Int'l Conference on Field-Programmable Technology , 2002 . J. Anderson, F. Najm, \"Power-Aware Technology Mapping for LUT-Based FPGAs\", Proc of Int'l Conference on Field-Programmable Technology, 2002."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/968280.968287"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/313817.313920"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/968280.968285"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/871506.871535"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382647"},{"key":"e_1_3_2_1_17_1","volume-title":"Proc. of Custom Integrated Circuits Conference","author":"Rahman A.","year":"2005","unstructured":"A. Rahman , S. Das , T. Tuan , A. Rahut , \" Heterogeneous Routing Architecture for Low Power FPGA Fabric\" , Proc. of Custom Integrated Circuits Conference , 2005 . A. Rahman, S. Das, T. Tuan, A. Rahut, \"Heterogeneous Routing Architecture for Low Power FPGA Fabric\", Proc. of Custom Integrated Circuits Conference, 2005."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/968280.968288"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996767"},{"key":"e_1_3_2_1_20_1","volume-title":"Proc of Int'l Conference on CAD","author":"Li F.","year":"2004","unstructured":"F. Li , Y. Lin , L. He , \" A Fully Vdd-Programmable Fabric for Low-Power FPGAs\" , Proc of Int'l Conference on CAD , 2004 . F. Li, Y. Lin, L. He, \"A Fully Vdd-Programmable Fabric for Low-Power FPGAs\", Proc of Int'l Conference on CAD, 2004."},{"key":"e_1_3_2_1_21_1","unstructured":"Xilinx Inc. Spartan-3 FPGA Family Datasheet http:\/\/www.xilinx.com.  Xilinx Inc. Spartan-3 FPGA Family Datasheet http:\/\/www.xilinx.com."},{"key":"e_1_3_2_1_22_1","volume-title":"Proc. of Custom Integrated Circuits Conference","author":"Tuan T.","year":"2003","unstructured":"T. Tuan , B. Lai , \" Leakage Power Analysis of a 90nm FPGA \", Proc. of Custom Integrated Circuits Conference , 2003 . T. Tuan, B. Lai, \"Leakage Power Analysis of a 90nm FPGA\", Proc. of Custom Integrated Circuits Conference, 2003."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/1120725.1120986"},{"key":"e_1_3_2_1_24_1","unstructured":"Xilinx Inc Virtex-4 FPGA Family Datasheet http:\/\/www.xilinx.com.  Xilinx Inc Virtex-4 FPGA Family Datasheet http:\/\/www.xilinx.com."}],"event":{"name":"FPGA06: ACM\/SIGDA International Symposium on Field Programmable Gate Arrays","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"],"location":"Monterey California USA","acronym":"FPGA06"},"container-title":["Proceedings of the 2006 ACM\/SIGDA 14th international symposium on Field programmable gate arrays"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1117201.1117203","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1117201.1117203","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T16:18:54Z","timestamp":1750263534000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1117201.1117203"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006,2,22]]},"references-count":24,"alternative-id":["10.1145\/1117201.1117203","10.1145\/1117201"],"URL":"https:\/\/doi.org\/10.1145\/1117201.1117203","relation":{},"subject":[],"published":{"date-parts":[[2006,2,22]]},"assertion":[{"value":"2006-02-22","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}