{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:42:37Z","timestamp":1750308157212,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":17,"publisher":"ACM","license":[{"start":{"date-parts":[[2006,3,4]],"date-time":"2006-03-04T00:00:00Z","timestamp":1141430400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2006,3,4]]},"DOI":"10.1145\/1117278.1117296","type":"proceedings-article","created":{"date-parts":[[2006,5,8]],"date-time":"2006-05-08T21:40:43Z","timestamp":1147124443000},"page":"85-90","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Impact of interconnect resistance increase on system performance of low power and high performance designs"],"prefix":"10.1145","author":[{"given":"Mandeep","family":"Bamal","sequence":"first","affiliation":[{"name":"IMEC, Kapeldreef 75, Leuven, Belgium and Katholieke Universiteit Leuven, Belgium"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Youssef","family":"Travaly","sequence":"additional","affiliation":[{"name":"IMEC, Kapeldreef 75, Leuven, Belgium"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wenqi","family":"Zhang","sequence":"additional","affiliation":[{"name":"IMEC, Kapeldreef 75, Leuven, Belgium and Katholieke Universiteit Leuven, Belgium"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michele","family":"Stucchi","sequence":"additional","affiliation":[{"name":"IMEC, Kapeldreef 75, Leuven, Belgium"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Karen","family":"Maex","sequence":"additional","affiliation":[{"name":"IMEC, Kapeldreef 75, Leuven, Belgium and Katholieke Universiteit Leuven, Belgium"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2006,3,4]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1017\/S0305004100019952"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1080\/00018735200101151"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevB.1.1382"},{"key":"e_1_3_2_1_4_1","unstructured":"International technology roadmap for semiconductors 2004.  International technology roadmap for semiconductors 2004."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.371970"},{"key":"e_1_3_2_1_6_1","volume-title":"Circuits, Interconnections and packaging for VLSI","author":"Bakoglu H. B.","year":"1990","unstructured":"H. B. Bakoglu , Circuits, Interconnections and packaging for VLSI , Reading, MA : Addison Wesley , 1990 . H. B. Bakoglu, Circuits, Interconnections and packaging for VLSI, Reading, MA: Addison Wesley, 1990."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.362754"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2005.1499978"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2005.1499976"},{"volume-title":"Synopsys","year":"2003","key":"e_1_3_2_1_10_1","unstructured":"Raphael - Interconnect analysis program , Synopsys , 2003 . Raphael - Interconnect analysis program, Synopsys, 2003."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/16.661219"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.902258"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.974903"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/288548.288614"},{"key":"e_1_3_2_1_15_1","first-page":"77","volume":"62","author":"Dingle R. B.","year":"1949","unstructured":"R. B. Dingle , Proc. Roy. Soc. , 62 , 77 ( 1949 ). R. B. Dingle, Proc. Roy. Soc., 62, 77 (1949).","journal-title":"Proc. Roy. Soc."},{"volume-title":"Bamal et al. \"A novel approach to resistivity and interconnect modeling\", submitted to MAM2006","author":"Travaly Y.","key":"e_1_3_2_1_16_1","unstructured":"Y. Travaly and M. Bamal et al. \"A novel approach to resistivity and interconnect modeling\", submitted to MAM2006 . Y. Travaly and M. Bamal et al. \"A novel approach to resistivity and interconnect modeling\", submitted to MAM2006."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/16.992867"}],"event":{"name":"SLIP06: International Workshop on System Level Interconnect Prediction","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"],"location":"Munich Germany","acronym":"SLIP06"},"container-title":["Proceedings of the 2006 international workshop on System-level interconnect prediction"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1117278.1117296","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1117278.1117296","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T16:18:55Z","timestamp":1750263535000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1117278.1117296"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006,3,4]]},"references-count":17,"alternative-id":["10.1145\/1117278.1117296","10.1145\/1117278"],"URL":"https:\/\/doi.org\/10.1145\/1117278.1117296","relation":{},"subject":[],"published":{"date-parts":[[2006,3,4]]},"assertion":[{"value":"2006-03-04","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}