{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T12:06:37Z","timestamp":1759147597639,"version":"3.41.0"},"reference-count":20,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2006,1,1]],"date-time":"2006-01-01T00:00:00Z","timestamp":1136073600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2006,1]]},"abstract":"<jats:p>The Cameron Project has developed a system for compiling codes written in a high-level language called SA-C, to FPGA-based reconfigurable computing systems. In order to exploit the parallelism available on the FPGAs, the SA-C compiler performs a large number of optimizations such as full loop unrolling, loop fusion and strip-mining. However, since the area on an FPGA is limited, the compiler needs to know the effect of compiler optimizations on the FPGA area; this information is typically not available until after the synthesis and place and route stage, which can take hours. In this article, we present a compile-time area estimation technique to guide SA-C compiler optimizations. We demonstrate our technique for a variety of benchmarks written in SA-C. Experimental results show that our technique predicts the area required for a design to within 2.5% of actual for small image processing operators and to within 5.0% for larger benchmarks. The estimation time is in the order of milliseconds, compared with minutes for the synthesis tool.<\/jats:p>","DOI":"10.1145\/1124713.1124721","type":"journal-article","created":{"date-parts":[[2006,5,8]],"date-time":"2006-05-08T16:09:20Z","timestamp":1147104560000},"page":"104-122","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":27,"title":["Compile-time area estimation for LUT-based FPGAs"],"prefix":"10.1145","volume":"11","author":[{"given":"Dhananjay","family":"Kulkarni","sequence":"first","affiliation":[{"name":"University of California, Riverside, Riverside, CA"}]},{"given":"Walid A.","family":"Najjar","sequence":"additional","affiliation":[{"name":"University of California, Riverside, Riverside, CA"}]},{"given":"Robert","family":"Rinker","sequence":"additional","affiliation":[{"name":"University of Idaho, Moscow, ID"}]},{"given":"Fadi J.","family":"Kurdahi","sequence":"additional","affiliation":[{"name":"University of California, Irvine, Irvine, CA"}]}],"member":"320","published-online":{"date-parts":[[2006,1]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"Annapolis Micro Systems 2000. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MD. www.annapmicro.com.]]  Annapolis Micro Systems Inc. 2000. WILDSTAR Reference Manual. Annapolis Micro Systems Inc. Annapolis MD. www.annapmicro.com.]]"},{"volume-title":"Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines. 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Computing Machines (FCCM)","author":"Kulkarni D.","key":"e_1_2_1_12_1"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2003.1220583"},{"volume-title":"Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)","author":"Ohm S.","key":"e_1_2_1_14_1"},{"volume-title":"Proceedings of the International Symposium on System Synthesis (ISSS).]] 10","author":"Ohm S.","key":"e_1_2_1_15_1"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.920828"},{"volume-title":"Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)","author":"Shayee K.","key":"e_1_2_1_17_1"},{"volume-title":"Proceedings of the IEEE Symposium on Field-Programmable Logic and Applications (FPGA 2000)","author":"Weis K.","key":"e_1_2_1_18_1"},{"key":"e_1_2_1_19_1","unstructured":"Xilinx Inc. 2000. Virtex 2.5V Field Progammable Gate Array. Xilinx Inc. www.xilinx.com.]]  Xilinx Inc. 2000. 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