{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:40:48Z","timestamp":1750308048857,"version":"3.41.0"},"reference-count":16,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2006,1,1]],"date-time":"2006-01-01T00:00:00Z","timestamp":1136073600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2006,1]]},"abstract":"<jats:p>For many embedded applications, program code size is a critical design factor. One promising approach for reducing code size is to employ a \u201cdual instruction set\u201d, where processor architectures support a normal (usually 32-bit) Instruction Set, and a narrow, space-efficient (usually 16-bit) Instruction Set with a limited set of opcodes and access to a limited set of registers. This feature however, requires compilers that can reduce code size by compiling for both Instruction Sets. Existing compiler techniques operate at the routine-level granularity and are unable to make the trade-off between increased register pressure (resulting in more spills) and decreased code size. We present a compilation framework for such dual instruction sets, which uses a profitability based compiler heuristic that operates at the instruction-level granularity and is able to effectively take advantage of both Instruction Sets. We demonstrate consistent and improved code size reduction (on average 22%), for the MIPS 32\/16 bit ISA. We also show that the code compression obtained by this \u201cdual instruction set\u201d technique is heavily dependent on the application characteristics and the narrow Instruction Set itself.<\/jats:p>","DOI":"10.1145\/1124713.1124722","type":"journal-article","created":{"date-parts":[[2006,5,8]],"date-time":"2006-05-08T16:09:20Z","timestamp":1147104560000},"page":"123-146","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":14,"title":["Compilation framework for code size reduction using reduced bit-width ISAs (rISAs)"],"prefix":"10.1145","volume":"11","author":[{"given":"Aviral","family":"Shrivastava","sequence":"first","affiliation":[{"name":"University of California, Irvine, Irvine, CA"}]},{"given":"Partha","family":"Biswas","sequence":"additional","affiliation":[{"name":"University of California, Irvine, Irvine, CA"}]},{"given":"Ashok","family":"Halambi","sequence":"additional","affiliation":[{"name":"University of California, Irvine, Irvine, CA"}]},{"given":"Nikil","family":"Dutt","sequence":"additional","affiliation":[{"name":"University of California, Irvine, Irvine, CA"}]},{"given":"Alex","family":"Nicolau","sequence":"additional","affiliation":[{"name":"University of California, Irvine, Irvine, CA"}]}],"member":"320","published-online":{"date-parts":[[2006,1]]},"reference":[{"volume-title":"Advanced RISC Machines","author":"Advanced RISC","key":"e_1_2_1_1_1","unstructured":"Advanced RISC Machines , Ltd. 2003. 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