{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:40:48Z","timestamp":1750308048299,"version":"3.41.0"},"reference-count":33,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2006,1,1]],"date-time":"2006-01-01T00:00:00Z","timestamp":1136073600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2006,1]]},"abstract":"<jats:p>In low-power design for battery-driven portable applications, the reduction of peak power, peak power differential, cycle difference power, average power and energy are equally important. These are different forms of dynamic power dissipation of a CMOS circuit, which is predominant compared to static power dissipation for higher switching activity. The peak power, the cycle difference power, and the peak power differential drive the transient characteristic of a CMOS circuit. In this article, we propose an ILP-based framework for the reduction of energy and transient power through datapath scheduling during behavioral synthesis. A new metric called \u201cmodified cycle power function\u201d (CPF*) is defined that captures the above power characteristics and facilitates integer linear programming formulations. The ILP-based datapath scheduling schemes with CPF* as objective function are developed assuming three modes of datapath operation, such as, single supply voltage and single frequency (SVSF), multiple supply voltages and dynamic frequency clocking (MVDFC), and multiple supply voltages and multicycling (MVMC). We conducted experiments on selected high-level synthesis benchmark circuits for various resource constraints and estimated power, energy and energy delay product for each of them. Experimental results show that significant reductions in power, energy and energy delay product can be obtained.<\/jats:p>","DOI":"10.1145\/1124713.1124725","type":"journal-article","created":{"date-parts":[[2006,5,8]],"date-time":"2006-05-08T16:09:20Z","timestamp":1147104560000},"page":"186-212","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["ILP models for simultaneous energy and transient power minimization during behavioral synthesis"],"prefix":"10.1145","volume":"11","author":[{"given":"Saraju P.","family":"Mohanty","sequence":"first","affiliation":[{"name":"University of North Texas, Denton, TX"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"N.","family":"Ranganathan","sequence":"additional","affiliation":[{"name":"University of South Florida, Tampa, FL"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sunil K.","family":"Chappidi","sequence":"additional","affiliation":[{"name":"University of South Florida, Tampa, FL"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2006,1]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.700720"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.795120"},{"volume-title":"Proceedings of the IEEE Custom Integrated Circuits Conference. IEEE Computer Society Press","author":"Brynjolfson I.","key":"e_1_2_1_3_1","unstructured":"Brynjolfson , I. and Zilic , Z . 2000. Dynamic clock management for low power applications in FPGAs . In Proceedings of the IEEE Custom Integrated Circuits Conference. IEEE Computer Society Press , Los Alamitos, CA, 139--142.]] Brynjolfson, I. and Zilic, Z. 2000. Dynamic clock management for low power applications in FPGAs. In Proceedings of the IEEE Custom Integrated Circuits Conference. IEEE Computer Society Press, Los Alamitos, CA, 139--142.]]"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.881202"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.645070"},{"key":"e_1_2_1_6_1","volume-title":"AMPL: A Modeling Language for Mathematical Programming. Thomson Brooks Cole.]]","author":"Fourer R.","year":"2003","unstructured":"Fourer , R. , Gay , D. , and Kernighan , B . 2003 . AMPL: A Modeling Language for Mathematical Programming. Thomson Brooks Cole.]] Fourer, R., Gay, D., and Kernighan, B. 2003. AMPL: A Modeling Language for Mathematical Programming. Thomson Brooks Cole.]]"},{"volume-title":"Proceedings of the Workshop on Power-Aware Computer Systems. 65--81","author":"Hsu C. H.","key":"e_1_2_1_7_1","unstructured":"Hsu , C. H. , Kremer , U. , and Hsiao , M . 2000. Compiler-directed dynamic frequency and voltage scheduling . In Proceedings of the Workshop on Power-Aware Computer Systems. 65--81 .]] Hsu, C. H., Kremer, U., and Hsiao, M. 2000. Compiler-directed dynamic frequency and voltage scheduling. In Proceedings of the Workshop on Power-Aware Computer Systems. 65--81.]]"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/264995.264997"},{"volume-title":"Proceedings of the IEEE International Symposium on Circuits and Systems. IEEE Computer Society Press","author":"Kim J. M.","key":"e_1_2_1_9_1","unstructured":"Kim , J. M. and Chae , S. I . 1996. New MPEG2 decoder architecture using frequency scaling . In Proceedings of the IEEE International Symposium on Circuits and Systems. IEEE Computer Society Press , Los Alamitos, CA, 253--256.]] Kim, J. M. and Chae, S. I. 1996. New MPEG2 decoder architecture using frequency scaling. In Proceedings of the IEEE International Symposium on Circuits and Systems. IEEE Computer Society Press, Los Alamitos, CA, 253--256.]]"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.386219"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.988725"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/54.500201"},{"key":"e_1_2_1_13_1","unstructured":"McCarl B. A. and Spreen T. H. 1997. Applied Mathematical Programming using Algebric Systems. Online Book at : http:\/\/agecon.tamu.edu\/faculty\/mccarl\/regbook.htm.]]  McCarl B. A. and Spreen T. H. 1997. Applied Mathematical Programming using Algebric Systems. Online Book at : http:\/\/agecon.tamu.edu\/faculty\/mccarl\/regbook.htm.]]"},{"volume-title":"Proceedings of the International Conference on VLSI Design. 539--545","author":"Mohanty S. P.","key":"e_1_2_1_14_1","unstructured":"Mohanty , S. P. and Ranganathan , N . 2003a. A framework for energy and transient power reduction during behavioral synthesis . In Proceedings of the International Conference on VLSI Design. 539--545 .]] Mohanty, S. P. and Ranganathan, N. 2003a. A framework for energy and transient power reduction during behavioral synthesis. In Proceedings of the International Conference on VLSI Design. 539--545.]]"},{"volume-title":"Proceedings of the International Conference on VLSI Design. 446--451","author":"Mohanty S. P.","key":"e_1_2_1_15_1","unstructured":"Mohanty , S. P. and Ranganathan , N . 2003b. Energy efficient scheduling for datapath synthesis . In Proceedings of the International Conference on VLSI Design. 446--451 .]] Mohanty, S. P. and Ranganathan, N. 2003b. Energy efficient scheduling for datapath synthesis. In Proceedings of the International Conference on VLSI Design. 446--451.]]"},{"volume-title":"Proceedings of the IEEE Computer Society Annual Symposium on VLSI. IEEE Computer Society Press","author":"Mohanty S. P.","key":"e_1_2_1_16_1","unstructured":"Mohanty , S. P. , Ranganathan , N. , and Chappidi , S. K . 2003. Peak power minimization through datapath scheduling . In Proceedings of the IEEE Computer Society Annual Symposium on VLSI. IEEE Computer Society Press , Los Alamitos, CA, 121--126.]] Mohanty, S. P., Ranganathan, N., and Chappidi, S. K. 2003. Peak power minimization through datapath scheduling. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI. IEEE Computer Society Press, Los Alamitos, CA, 121--126.]]"},{"volume-title":"Proceedings of the IEEE Computer Society Annual Symposium on VLSI. IEEE Computer Society Press","author":"Mohanty S. P.","key":"e_1_2_1_17_1","unstructured":"Mohanty , S. P. , Ranganathan , N. , and Krishna , V . 2002. Datapath scheduling using dynamic frequency clocking . In Proceedings of the IEEE Computer Society Annual Symposium on VLSI. IEEE Computer Society Press , Los Alamitos, CA, 65--70.]] Mohanty, S. P., Ranganathan, N., and Krishna, V. 2002. Datapath scheduling using dynamic frequency clocking. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI. IEEE Computer Society Press, Los Alamitos, CA, 65--70.]]"},{"key":"e_1_2_1_18_1","volume-title":"Linear Programming: Mathematics, Theory and Practice","author":"Panik M. J.","year":"1996","unstructured":"Panik , M. J. 1996 . Linear Programming: Mathematics, Theory and Practice . Kluwer Academic Publishers .]] Panik, M. J. 1996. Linear Programming: Mathematics, Theory and Practice. Kluwer Academic Publishers.]]"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.766754"},{"key":"e_1_2_1_20_1","first-page":"2","article-title":"Performance-driven high-level synthesis with bit-level chaining and clock selection","volume":"20","author":"Park S.","year":"2001","unstructured":"Park , S. and Choi , K. 2001 . Performance-driven high-level synthesis with bit-level chaining and clock selection . IEEE Trans. Computer-Aided Des. Integr. Circ. Syst. 20 , 2 (Feb.), 199--212.]] Park, S. and Choi, K. 2001. Performance-driven high-level synthesis with bit-level chaining and clock selection. IEEE Trans. Computer-Aided Des. Integr. Circ. Syst. 20, 2 (Feb.), 199--212.]]","journal-title":"IEEE Trans. Computer-Aided Des. Integr. Circ. Syst."},{"volume-title":"Proceedings of the International Symposium on Low Power Electronics and Design. 28--33","author":"Pouwelse J.","key":"e_1_2_1_21_1","unstructured":"Pouwelse , J. , Langendoen , K. , and Sips , H . 2001. Energy priority scheduling for variable voltage processor . In Proceedings of the International Symposium on Low Power Electronics and Design. 28--33 .]] 10.1145\/383082.383089 Pouwelse, J., Langendoen, K., and Sips, H. 2001. Energy priority scheduling for variable voltage processor. In Proceedings of the International Symposium on Low Power Electronics and Design. 28--33.]] 10.1145\/383082.383089"},{"key":"e_1_2_1_22_1","doi-asserted-by":"crossref","first-page":"11","DOI":"10.1109\/43.663817","article-title":"SCALP: An iterative-improvement based low-power data- path synthesis system","volume":"16","author":"Raghunathan A.","year":"1997","unstructured":"Raghunathan , A. and Jha , N. K. 1997 . SCALP: An iterative-improvement based low-power data- path synthesis system . IEEE Trans. CAD Integ. Circ. Syst. 16 , 11 (Nov.), 1260--1277.]] Raghunathan, A. and Jha, N. K. 1997. SCALP: An iterative-improvement based low-power data- path synthesis system. IEEE Trans. CAD Integ. Circ. Syst. 16, 11 (Nov.), 1260--1277.]]","journal-title":"IEEE Trans. CAD Integ. Circ. Syst."},{"volume-title":"Proceedings of the International Conference on Computer Aided Design. 545--552","author":"Raghunathan V.","key":"e_1_2_1_23_1","unstructured":"Raghunathan , V. , Ravi , S. , Raghunathan , A. , and Lakshminarayana , G . 2001. Transient power management through high level synthesis . In Proceedings of the International Conference on Computer Aided Design. 545--552 .]] Raghunathan, V., Ravi, S., Raghunathan, A., and Lakshminarayana, G. 2001. Transient power management through high level synthesis. In Proceedings of the International Conference on Computer Aided Design. 545--552.]]"},{"key":"e_1_2_1_24_1","doi-asserted-by":"crossref","first-page":"7","DOI":"10.1109\/43.644033","article-title":"Analytical estimation of signal transition activity from word-level statistics","volume":"16","author":"Ramprasad S.","year":"1997","unstructured":"Ramprasad , S. , Shanbhag , N. R. , and Hajj , I. N. 1997 . Analytical estimation of signal transition activity from word-level statistics . IEEE Trans. CAD Integ. Circ. Syst. 16 , 7 (July), 718--733.]] Ramprasad, S., Shanbhag, N. R., and Hajj, I. N. 1997. Analytical estimation of signal transition activity from word-level statistics. IEEE Trans. CAD Integ. Circ. Syst. 16, 7 (July), 718--733.]]","journal-title":"IEEE Trans. CAD Integ. Circ. Syst."},{"volume-title":"Proceedings of the International Conference on Computer Design. 137--140","author":"Ranganathan N.","key":"e_1_2_1_25_1","unstructured":"Ranganathan , N. , Vijaykrishnan , N. , and Bhavanishankar , N . 1996. A VLSI array architecture with dynamic frequency clocking . In Proceedings of the International Conference on Computer Design. 137--140 .]] Ranganathan, N., Vijaykrishnan, N., and Bhavanishankar, N. 1996. A VLSI array architecture with dynamic frequency clocking. In Proceedings of the International Conference on Computer Design. 137--140.]]"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/76.709410"},{"key":"e_1_2_1_27_1","volume-title":"Engineering Optimization: Theory and Practice","author":"Rao S. S.","year":"1996","unstructured":"Rao , S. S. 1996 . Engineering Optimization: Theory and Practice . Addison-Wesley , Reading, MA .]] Rao, S. S. 1996. Engineering Optimization: Theory and Practice. Addison-Wesley, Reading, MA.]]"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.831435"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2000.862382"},{"volume-title":"Proceedings of the IEEE International Symposium on Circuits and Systems (Vol. 3). IEEE Computer Society Press","author":"Shiue W. T.","key":"e_1_2_1_30_1","unstructured":"Shiue , W. T. and Chakrabarti , C . 2000a. ILP based scheme for low power scheduling and resource binding . In Proceedings of the IEEE International Symposium on Circuits and Systems (Vol. 3). IEEE Computer Society Press , Los Alamitos, CA, 279--282.]] Shiue, W. T. and Chakrabarti, C. 2000a. ILP based scheme for low power scheduling and resource binding. In Proceedings of the IEEE International Symposium on Circuits and Systems (Vol. 3). IEEE Computer Society Press, Los Alamitos, CA, 279--282.]]"},{"key":"e_1_2_1_31_1","first-page":"6","article-title":"Low-power scheduling with resources operating at multiple voltages","volume":"47","author":"Shiue W. T.","year":"2000","unstructured":"Shiue , W. T. and Chakrabarti , C. 2000 b. Low-power scheduling with resources operating at multiple voltages . IEEE Trans. Circ. Syst.-II : Anal. Digit. Sig. Proc. 47 , 6 (June), 536--543.]] Shiue, W. T. and Chakrabarti, C. 2000b. Low-power scheduling with resources operating at multiple voltages. IEEE Trans. Circ. Syst.-II : Anal. Digit. Sig. Proc. 47, 6 (June), 536--543.]]","journal-title":"IEEE Trans. Circ. Syst.-II : Anal. Digit. Sig. Proc."},{"volume-title":"Proceedings of the 43rd Midwest Symposium on Circuits and Systems. 312--315","author":"Shiue W. T.","key":"e_1_2_1_32_1","unstructured":"Shiue , W. T. , Denison , J. , and Horak , A . 2000. A novel scheduler for low power real time systems . In Proceedings of the 43rd Midwest Symposium on Circuits and Systems. 312--315 .]] Shiue, W. T., Denison, J., and Horak, A. 2000. A novel scheduler for low power real time systems. In Proceedings of the 43rd Midwest Symposium on Circuits and Systems. 312--315.]]"},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.371967"}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1124713.1124725","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1124713.1124725","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T15:14:35Z","timestamp":1750259675000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1124713.1124725"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006,1]]},"references-count":33,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2006,1]]}},"alternative-id":["10.1145\/1124713.1124725"],"URL":"https:\/\/doi.org\/10.1145\/1124713.1124725","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"type":"print","value":"1084-4309"},{"type":"electronic","value":"1557-7309"}],"subject":[],"published":{"date-parts":[[2006,1]]},"assertion":[{"value":"2006-01-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}