{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:39:55Z","timestamp":1750307995047,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":10,"publisher":"ACM","license":[{"start":{"date-parts":[[2006,4,30]],"date-time":"2006-04-30T00:00:00Z","timestamp":1146355200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2006,4,30]]},"DOI":"10.1145\/1127908.1127936","type":"proceedings-article","created":{"date-parts":[[2006,5,8]],"date-time":"2006-05-08T21:40:43Z","timestamp":1147124443000},"page":"111-114","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Efficient encoding for address buses with temporal redundancy for simultaneous area and energy reduction"],"prefix":"10.1145","author":[{"given":"Jiangjiang","family":"Liu","sequence":"first","affiliation":[{"name":"Lamar University, Beaumont, TX"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Krishnan","family":"Sundaresan","sequence":"additional","affiliation":[{"name":"Michigan State University, East Lansing, MI"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nihar R.","family":"Mahapatra","sequence":"additional","affiliation":[{"name":"Michigan State University, East Lansing, MI"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2006,4,30]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"201","volume-title":"Proceedings of the IEEE Custom Integrated Circuits Conference","author":"Cao Y.","year":"2000","unstructured":"Y. Cao , T. Sato , D. Sylvester , M. Orshansky , and C. Hu . New Paradigm of Predictive MOSFET and Interconnect Modeling for Early Circuit Design . In Proceedings of the IEEE Custom Integrated Circuits Conference , pages 201 -- 204 , June 2000 . Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu. New Paradigm of Predictive MOSFET and Interconnect Modeling for Early Circuit Design. In Proceedings of the IEEE Custom Integrated Circuits Conference, pages 201--204, June 2000."},{"key":"e_1_3_2_1_2_1","volume-title":"Proceedings of International Symposium on Quality of Electronics Design","author":"Cheng W.C.","year":"2001","unstructured":"W.C. Cheng and M. Pedram . Memory Bus Encoding for Low-Power: A Tutorial . In Proceedings of International Symposium on Quality of Electronics Design , March 2001 . W.C. Cheng and M. Pedram. Memory Bus Encoding for Low-Power: A Tutorial. In Proceedings of International Symposium on Quality of Electronics Design, March 2001."},{"key":"e_1_3_2_1_4_1","first-page":"220","volume-title":"Proceedings of the IEEE Computer Society Annual Symposium on VLSI","author":"Liu J.","year":"2003","unstructured":"J. Liu , N.R. Mahapatra , and K. Sundaresan . Hardware-Only Compression to Reduce Cost and Improve Utilization of Address Buses . In Proceedings of the IEEE Computer Society Annual Symposium on VLSI , pages 220 -- 221 , February 2003 . J. Liu, N.R. Mahapatra, and K. Sundaresan. Hardware-Only Compression to Reduce Cost and Improve Utilization of Address Buses. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI, pages 220--221, February 2003."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/966747.966750"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.5555\/946246.946519"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.736129"},{"key":"e_1_3_2_1_8_1","first-page":"414","volume-title":"Proceedings of Custom Integrated Circuits Conference","author":"Sotiriadis P.P.","year":"2000","unstructured":"P.P. Sotiriadis and A. Chandrakasan . Low Power Bus Coding Techniques Considering Inter-Wire Capacitances . In Proceedings of Custom Integrated Circuits Conference , pages 414 -- 419 , May 2000 . P.P. Sotiriadis and A. Chandrakasan. Low Power Bus Coding Techniques Considering Inter-Wire Capacitances. In Proceedings of Custom Integrated Circuits Conference, pages 414--419, May 2000."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.365453"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/566408.566431"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379058"}],"event":{"name":"GLSVLSI06: Great Lakes Symposium on VLSI 2006","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"],"location":"Philadelphia PA USA","acronym":"GLSVLSI06"},"container-title":["Proceedings of the 16th ACM Great Lakes symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1127908.1127936","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1127908.1127936","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T15:06:20Z","timestamp":1750259180000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1127908.1127936"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006,4,30]]},"references-count":10,"alternative-id":["10.1145\/1127908.1127936","10.1145\/1127908"],"URL":"https:\/\/doi.org\/10.1145\/1127908.1127936","relation":{},"subject":[],"published":{"date-parts":[[2006,4,30]]},"assertion":[{"value":"2006-04-30","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}