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In this paper, we present an IP design approach that relies on three main phases: (1) constraint modeling, (2) IP constraint analysis steps for feasibility checking, and (3) synthesis. We propose a set of techniques dedicated to the digital signal processing domain that lead to an optimized IP core integration. Based on a generic architecture of components, the method we propose provides automatic generation of IP cores designed under integration constraints. We show the effectiveness of our approach with a DCT core design case study.<\/jats:p>","DOI":"10.1145\/1132357.1132359","type":"journal-article","created":{"date-parts":[[2006,7,25]],"date-time":"2006-07-25T14:14:26Z","timestamp":1153836866000},"page":"29-53","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":16,"title":["A formal method for hardware IP design and integration under I\/O and timing constraints"],"prefix":"10.1145","volume":"5","author":[{"given":"Philippe","family":"Coussy","sequence":"first","affiliation":[{"name":"UBS University, Lorient Cedex, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Emmanuel","family":"Casseau","sequence":"additional","affiliation":[{"name":"UBS University, Lorient Cedex, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pierre","family":"Bomel","sequence":"additional","affiliation":[{"name":"UBS University, Lorient Cedex, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Adel","family":"Baganne","sequence":"additional","affiliation":[{"name":"UBS University, Lorient Cedex, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Eric","family":"Martin","sequence":"additional","affiliation":[{"name":"UBS University, Lorient Cedex, France"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2006,2]]},"reference":[{"volume-title":"ICM04 International Conference on Microelectronics, Tunis.","author":"Abbes F.","key":"e_1_2_1_1_1","unstructured":"Abbes , F. , Casseau , E. , Abid , M. , Coussy , P. , and Legof , J. B . 2004. IP integration methodology for SoC design . In ICM04 International Conference on Microelectronics, Tunis. Abbes, F., Casseau, E., Abid, M., Coussy, P., and Legof, J. B. 2004. IP integration methodology for SoC design. In ICM04 International Conference on Microelectronics, Tunis."},{"key":"e_1_2_1_2_1","first-page":"5","article-title":"A formal technique for hardware interface design","volume":"45","author":"Baganne A.","year":"1998","unstructured":"Baganne , A. , Philippe , J. L. , and Martin , E. 1998 . A formal technique for hardware interface design . In IEEE Trans. On Circuits and Systems 45 , 5 . Baganne, A., Philippe, J. L., and Martin, E. 1998. A formal technique for hardware interface design. In IEEE Trans. On Circuits and Systems 45, 5.","journal-title":"IEEE Trans. On Circuits and Systems"},{"key":"e_1_2_1_3_1","doi-asserted-by":"crossref","unstructured":"Ben ismail T. Daveau J.-M. O'brien K. and Jerraya A. A. 1996. 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In Proceedings of the IEEE International Conference on Design Automation and Test in Europe (DATE). 275--281."},{"volume-title":"Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD). 274--277","author":"Boriello G.","key":"e_1_2_1_5_1","unstructured":"Boriello , G. and Katz , R. H . 1987. Synthesis and optimization of interface transducer logic . In Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD). 274--277 . Boriello, G. and Katz, R. H. 1987. Synthesis and optimization of interface transducer logic. In Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD). 274--277."},{"key":"e_1_2_1_6_1","unstructured":"Chang H. Cooke L. Hunt M. Martin G. McNelly A. J. and Todd L. 1999. Surviving the SoC Revolution: A Guide to platform-based design. Kluwer Academic Publ. Boston MA.   Chang H. Cooke L. Hunt M. Martin G. McNelly A. J. and Todd L. 1999. Surviving the SoC Revolution: A Guide to platform-based design. Kluwer Academic Publ. Boston MA."},{"key":"e_1_2_1_7_1","doi-asserted-by":"crossref","unstructured":"Cathoor F. Wuytack S. De Greef E. Balassa F. Nachtergale L. and Vandecappelle A. 1998. Custom Memory Management Methodology. Kluwer Academic Publ. Boston MA.   Cathoor F. Wuytack S. De Greef E. Balassa F. Nachtergale L. and Vandecappelle A. 1998. Custom Memory Management Methodology. Kluwer Academic Publ. Boston MA.","DOI":"10.1007\/978-1-4757-2849-1"},{"volume-title":"Proceedings of the IEEE International Workshop on Hardware\/Software Co-Design (CODES).","author":"Chiodo M.","key":"e_1_2_1_8_1","unstructured":"Chiodo , M. , Giuspo , P. , and Jurecska , A . 1993. Synthesis of mixed software-hardware implementations from CFSM specifications . In Proceedings of the IEEE International Workshop on Hardware\/Software Co-Design (CODES). Chiodo, M., Giuspo, P., and Jurecska, A. 1993. Synthesis of mixed software-hardware implementations from CFSM specifications. In Proceedings of the IEEE International Workshop on Hardware\/Software Co-Design (CODES)."},{"key":"e_1_2_1_9_1","volume-title":"Proceedings of the IEEE International Design Automation Conference (DAC). 10","author":"Chou P.","year":"1962","unstructured":"Chou , P. and Borriello , G . 1994. Software scheduling in the co-synthesis of reactive real-time systems . In Proceedings of the IEEE International Design Automation Conference (DAC). 10 .1145\/ 1962 44.196247 Chou, P. and Borriello, G. 1994. Software scheduling in the co-synthesis of reactive real-time systems. In Proceedings of the IEEE International Design Automation Conference (DAC). 10.1145\/196244.196247"},{"volume-title":"Proceedings of the IEEE International Design Automation Conference (DAC). 10","author":"Chou P.","key":"e_1_2_1_10_1","unstructured":"Chou , P. and Borriello , G . 1995. Software interval scheduling: Fine-grained code scheduling for embedded systems . In Proceedings of the IEEE International Design Automation Conference (DAC). 10 .1145\/217474.217571 Chou, P. and Borriello, G. 1995. Software interval scheduling: Fine-grained code scheduling for embedded systems. In Proceedings of the IEEE International Design Automation Conference (DAC). 10.1145\/217474.217571"},{"volume-title":"Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD). 280--287","author":"Chou P.","key":"e_1_2_1_11_1","unstructured":"Chou , P. , Ortega , R. , and Borriello , G . 1995. Interface co-synthesis techniques for embedded systems . In Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD). 280--287 . Chou, P., Ortega, R., and Borriello, G. 1995. Interface co-synthesis techniques for embedded systems. In Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD). 280--287."},{"volume-title":"Proceedings of the IEEE Great Lakes Symposium on VLSI (GLSVLSI)","author":"Corre G.","key":"e_1_2_1_12_1","unstructured":"Corre , G. , Senn , E. , Julien , N. , and Martin , E . 2004. A memory aware behavioral synthesis tool for real-time VLSI circuits . In Proceedings of the IEEE Great Lakes Symposium on VLSI (GLSVLSI) , Boston, MA. 10.1145\/988952.988972 Corre, G., Senn, E., Julien, N., and Martin, E. 2004. A memory aware behavioral synthesis tool for real-time VLSI circuits. In Proceedings of the IEEE Great Lakes Symposium on VLSI (GLSVLSI), Boston, MA. 10.1145\/988952.988972"},{"volume-title":"Proceedings of IEEE International Symposium on Circuits and Systems ISCAS","author":"Coussy P.","key":"e_1_2_1_13_1","unstructured":"Coussy , P. , Baganne , A. , and Martin , E . 2002. A design methodology for IP integration . In Proceedings of IEEE International Symposium on Circuits and Systems ISCAS , Scottsdale, Arizona. Coussy, P., Baganne, A., and Martin, E. 2002. A design methodology for IP integration. In Proceedings of IEEE International Symposium on Circuits and Systems ISCAS, Scottsdale, Arizona."},{"volume-title":"Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).","author":"Coussy P.","key":"e_1_2_1_14_1","unstructured":"Coussy , P. , Gnaedig , D. , Nafkha , A. , Baganne , A. , Boutillon , E. , and Martin , E . 2004. A methodology for IP integration into DSP SoC: A case study of a MAP algorithm for turbo decoder . In Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP). Coussy, P., Gnaedig, D., Nafkha, A., Baganne, A., Boutillon, E., and Martin, E. 2004. A methodology for IP integration into DSP SoC: A case study of a MAP algorithm for turbo decoder. In Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)."},{"key":"e_1_2_1_15_1","volume-title":"Proceedings of the International Conference on Acoustics, Speech, and Signal Processing (ICASSP) 2001","author":"Cuesta F.","year":"2001","unstructured":"Cuesta , F. , Auguin , M. , Gresset , E. , and Capella , L . 2001. CODEF: A system level design space exploration tool . In Proceedings of the International Conference on Acoustics, Speech, and Signal Processing (ICASSP) 2001 , Salt Lake City, UT. May 7--12. 10.1109\/ICASSP. 2001 .941124 Cuesta, F., Auguin, M., Gresset, E., and Capella, L. 2001. CODEF: A system level design space exploration tool. In Proceedings of the International Conference on Acoustics, Speech, and Signal Processing (ICASSP) 2001, Salt Lake City, UT. May 7--12. 10.1109\/ICASSP.2001.941124"},{"volume-title":"Proceedings of IEEE International Workshop on Hardware\/Software Co-Design (CODES).","author":"Daveau J. M.","key":"e_1_2_1_16_1","unstructured":"Daveau , J. M. , Fernandes Marchioro G. , Ben-Ismail , T. , and Jerraya , A. A . 2001. Protocol selection and interface generation . In Proceedings of IEEE International Workshop on Hardware\/Software Co-Design (CODES). Daveau, J. M., Fernandes Marchioro G., Ben-Ismail, T., and Jerraya, A. A. 2001. Protocol selection and interface generation. In Proceedings of IEEE International Workshop on Hardware\/Software Co-Design (CODES)."},{"key":"e_1_2_1_17_1","volume-title":"Proceedings of the IEEE International Conference on Design Automation and Test in Europe (DATE).","author":"Deb A.","year":"2004","unstructured":"Deb , A. , Jantsch , A. , and \u00d6berg , J. 2004 . System design for DSP applications using the MASIC methodology . In Proceedings of the IEEE International Conference on Design Automation and Test in Europe (DATE). Deb, A., Jantsch, A., and \u00d6berg, J. 2004. System design for DSP applications using the MASIC methodology. In Proceedings of the IEEE International Conference on Design Automation and Test in Europe (DATE)."},{"volume-title":"Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD).","author":"Dey S.","key":"e_1_2_1_18_1","unstructured":"Dey , S. and Bommu , S . 1997. Performance analysis of a system of communicating processes . In Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD). Dey, S. and Bommu, S. 1997. Performance analysis of a system of communicating processes. In Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD)."},{"volume-title":"Understanding Behavioral Synthesis. A Practical Guide to High-Level Design","author":"Elliott J. P.","key":"e_1_2_1_19_1","unstructured":"Elliott , J. P. 2000. Understanding Behavioral Synthesis. A Practical Guide to High-Level Design . Kluwer Academic Publ . Boston, MA. Elliott, J. P. 2000. Understanding Behavioral Synthesis. A Practical Guide to High-Level Design. Kluwer Academic Publ. Boston, MA."},{"volume-title":"Interface optimization for concurrent systems under timing constraints","author":"Filo D.","key":"e_1_2_1_20_1","unstructured":"Filo , D. , Ku , D. , Coelho , C. N. , and De Micheli , G. 1993. Interface optimization for concurrent systems under timing constraints . In IEEE Transaction on VLSI systems. 268--281. Filo, D., Ku, D., Coelho, C. N., and De Micheli, G. 1993. Interface optimization for concurrent systems under timing constraints. In IEEE Transaction on VLSI systems. 268--281."},{"volume-title":"Proceedings of the IEEE International Symposiums on System Synthesis (ISSS).","author":"Freund L.","key":"e_1_2_1_21_1","unstructured":"Freund , L. , Isra\u00ebl , M. , Rousseau , F. , Berg\u00e9 , J. M. , Auguin , M. , Belleudy , C. , and Gogniat , G . 1996. A codesign experiment in acoustic echo cancellation: Gmdf &alpha; . In Proceedings of the IEEE International Symposiums on System Synthesis (ISSS). Freund, L., Isra\u00ebl, M., Rousseau, F., Berg\u00e9, J. M., Auguin, M., Belleudy, C., and Gogniat, G. 1996. A codesign experiment in acoustic echo cancellation: Gmdf &alpha;. In Proceedings of the IEEE International Symposiums on System Synthesis (ISSS)."},{"volume-title":"SpecC: Specification Language and Methodology","author":"Gajski D.","key":"e_1_2_1_22_1","unstructured":"Gajski , D. , SpecC: Specification Language and Methodology . Kluwer Academic Publ . Boston, MA. Gajski, D., et al. 2000. SpecC: Specification Language and Methodology. Kluwer Academic Publ. Boston, MA."},{"key":"e_1_2_1_23_1","volume-title":"High-level Synthesis: Introduction to Chip and System Design","author":"Gajski D.","year":"1991","unstructured":"Gajski , D. , 1991 . High-level Synthesis: Introduction to Chip and System Design . Kluwer Academic Publ . Boston, MA. Gajski, D., et al. 1991. High-level Synthesis: Introduction to Chip and System Design. Kluwer Academic Publ. Boston, MA."},{"key":"e_1_2_1_24_1","unstructured":"Gaut tool. 2004. http:\/\/lester.univ-ubs.fr\/tools\/gaut\/tool.htm.  Gaut tool. 2004. http:\/\/lester.univ-ubs.fr\/tools\/gaut\/tool.htm."},{"volume-title":"Proceedings of the 6th International Workshop on Hardware\/Software Codesign (CODES)","author":"Gogniat G.","key":"e_1_2_1_25_1","unstructured":"Gogniat , G. , Auguin , M. , Bianco , L. , and Pegatoquet , A . 1998. Communication synthesis and HW\/SW integration for embedded system design . In Proceedings of the 6th International Workshop on Hardware\/Software Codesign (CODES) , Seattle, WA, March 15--18. Gogniat, G., Auguin, M., Bianco, L., and Pegatoquet, A. 1998. Communication synthesis and HW\/SW integration for embedded system design. In Proceedings of the 6th International Workshop on Hardware\/Software Codesign (CODES), Seattle, WA, March 15--18."},{"volume-title":"Proceedings of the IEEE International Conference on Design Automation and Test in Europe (DATE).","author":"Gong J.","key":"e_1_2_1_26_1","unstructured":"Gong , J. , Gajski , D. , and Bakshi , S . 1996. Model refinement for hardware\/software codesign . In Proceedings of the IEEE International Conference on Design Automation and Test in Europe (DATE). Gong, J., Gajski, D., and Bakshi, S. 1996. Model refinement for hardware\/software codesign. In Proceedings of the IEEE International Conference on Design Automation and Test in Europe (DATE)."},{"volume-title":"Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD). 96--100","author":"Henkel J.","key":"e_1_2_1_28_1","unstructured":"Henkel , J. , Ernst , R. , Holtman , U. , and Benner , T . 1994. Adaptation of partitioning and high level synthesis in hardware\/software co-synthesis . In Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD). 96--100 . Henkel, J., Ernst, R., Holtman, U., and Benner, T. 1994. Adaptation of partitioning and high level synthesis in hardware\/software co-synthesis. In Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD). 96--100."},{"volume-title":"Proceedings of the 9th IEEE International Symposium on Hardware\/Software Co-design CODES","author":"Hommais D.","key":"e_1_2_1_29_1","unstructured":"Hommais , D. , P\u00e9trot , F. , and Aug\u00e9 , I . 2001. A practical toolbox for system level communication synthesis . In Proceedings of the 9th IEEE International Symposium on Hardware\/Software Co-design CODES . Copenhagen, Denmark. 10.1145\/371636.371674 Hommais, D., P\u00e9trot, F., and Aug\u00e9, I. 2001. A practical toolbox for system level communication synthesis. In Proceedings of the 9th IEEE International Symposium on Hardware\/Software Co-design CODES. Copenhagen, Denmark. 10.1145\/371636.371674"},{"volume-title":"Proceedings of the IEEE International Design Automation Conference (DAC). 10","author":"Jersak M.","key":"e_1_2_1_30_1","unstructured":"Jersak , M. and Ernst , E . 2003. Enabling scheduling analysis of heterogeneous systems with multi-rate data dependencies and rate intervals . In Proceedings of the IEEE International Design Automation Conference (DAC). 10 .1145\/775832.775951 Jersak, M. and Ernst, E. 2003. Enabling scheduling analysis of heterogeneous systems with multi-rate data dependencies and rate intervals. In Proceedings of the IEEE International Design Automation Conference (DAC). 10.1145\/775832.775951"},{"key":"e_1_2_1_31_1","volume-title":"Proceedings of the IEEE International Design Automation Conference (DAC). 10","author":"Knapp D.","year":"1995","unstructured":"Knapp , D. , Lyand , T. , 1995 . Behavioral synthesis methodology for HDL-based specification and validation . In Proceedings of the IEEE International Design Automation Conference (DAC). 10 .1145\/217474.217543 Knapp, D., Lyand, T., et al. 1995. Behavioral synthesis methodology for HDL-based specification and validation. In Proceedings of the IEEE International Design Automation Conference (DAC). 10.1145\/217474.217543"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.775629"},{"key":"e_1_2_1_33_1","first-page":"696","article-title":"Relative scheduling under timing constraints: Algorithms for high-level synthesis of digital circuits","volume":"11","author":"Ku D.","year":"1992","unstructured":"Ku , D. and De Micheli , G. 1992 . Relative scheduling under timing constraints: Algorithms for high-level synthesis of digital circuits . IEEE Transactions on CAD\/ICAS 11 , 696 -- 718 . Ku, D. and De Micheli, G. 1992. Relative scheduling under timing constraints: Algorithms for high-level synthesis of digital circuits. IEEE Transactions on CAD\/ICAS 11, 696--718.","journal-title":"IEEE Transactions on CAD\/ICAS"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.924830"},{"key":"e_1_2_1_35_1","first-page":"62","article-title":"An algorithm to compact VLSI symbolic layout with mixed constraints","volume":"2","author":"Liao Y.","year":"1983","unstructured":"Liao , Y. and Wong , C. 1983 . An algorithm to compact VLSI symbolic layout with mixed constraints . In IEEE Transaction on CAD\/ICAS 2 , 62 -- 69 . Liao, Y. and Wong, C. 1983. An algorithm to compact VLSI symbolic layout with mixed constraints. In IEEE Transaction on CAD\/ICAS 2, 62--69.","journal-title":"IEEE Transaction on CAD\/ICAS"},{"volume-title":"Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD).","author":"Lin B.","key":"e_1_2_1_36_1","unstructured":"Lin , B. and Vercauteren , S . 1994. Synthesis of concurrent system interface modules with automatic protocol conversion generation . In Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD). Lin, B. and Vercauteren, S. 1994. Synthesis of concurrent system interface modules with automatic protocol conversion generation. In Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD)."},{"key":"e_1_2_1_37_1","volume-title":"Proceedings of the IEEE International Design Automation Conference (DAC). 10","author":"Ly T.","year":"1995","unstructured":"Ly , T. , Knapp , D. , Miller , R. , and MacMillen , D. 1995 . Scheduling using behavioral templates . In Proceedings of the IEEE International Design Automation Conference (DAC). 10 .1145\/217474.217514 Ly, T., Knapp, D., Miller, R., and MacMillen, D. 1995. Scheduling using behavioral templates. In Proceedings of the IEEE International Design Automation Conference (DAC). 10.1145\/217474.217514"},{"volume-title":"Proceedings of the IEEE International Conference on Computer Design on VLSI in Computers & Processors (ICCD).","author":"McMillan K. L.","key":"e_1_2_1_38_1","unstructured":"McMillan , K. L. and Dill , D. L . 1992. Algorithms for interface timing verification . In Proceedings of the IEEE International Conference on Computer Design on VLSI in Computers & Processors (ICCD). McMillan, K. L. and Dill, D. L. 1992. Algorithms for interface timing verification. In Proceedings of the IEEE International Conference on Computer Design on VLSI in Computers & Processors (ICCD)."},{"volume-title":"Proceedings of the IEEE International Symposiums on System Synthesis (ISSS). 16--21","author":"Madsen J.","key":"e_1_2_1_39_1","unstructured":"Madsen , J. and Hald , B . 1995. An approach to interface synthesis . In Proceedings of the IEEE International Symposiums on System Synthesis (ISSS). 16--21 . 10.1145\/224486.224490 Madsen, J. and Hald, B. 1995. An approach to interface synthesis. In Proceedings of the IEEE International Symposiums on System Synthesis (ISSS). 16--21. 10.1145\/224486.224490"},{"key":"e_1_2_1_40_1","unstructured":"MPEG-2 ISO\/IEC JTC1\/SC29\/WG11 N0702. 1994. Rev. Information technology--Generic coding of moving pictures and associated audio recommendation H.262.  MPEG-2 ISO\/IEC JTC1\/SC29\/WG11 N0702. 1994. Rev. Information technology--Generic coding of moving pictures and associated audio recommendation H.262."},{"volume-title":"Proceedings of the IEEE International European Design Automation Conference (Euro DAC). 395--399","author":"Narayan S.","key":"e_1_2_1_41_1","unstructured":"Narayan , S. and Gajski , D . 1994. Synthesis of system-level bus interface . In Proceedings of the IEEE International European Design Automation Conference (Euro DAC). 395--399 . Narayan, S. and Gajski, D. 1994. Synthesis of system-level bus interface. In Proceedings of the IEEE International European Design Automation Conference (Euro DAC). 395--399."},{"volume-title":"Proceedings of the IEEE International Design Automation Conference (DAC). 468--473","author":"Narayan S.","key":"e_1_2_1_42_1","unstructured":"Narayan , S. and Gajski , D . 1995. Interfacing incompatible protocols using interface process generation . In Proceedings of the IEEE International Design Automation Conference (DAC). 468--473 . 10.1145\/217474.217572 Narayan, S. and Gajski, D. 1995. Interfacing incompatible protocols using interface process generation. In Proceedings of the IEEE International Design Automation Conference (DAC). 468--473. 10.1145\/217474.217572"},{"volume-title":"Proceedings of the IEEE International Design Automation Conference (DAC). 112--115","author":"Nestor J.","key":"e_1_2_1_43_1","unstructured":"Nestor , J. and Thomas , D . 1986. Behavioral synthesis with interfaces . In Proceedings of the IEEE International Design Automation Conference (DAC). 112--115 . Nestor, J. and Thomas, D. 1986. Behavioral synthesis with interfaces. In Proceedings of the IEEE International Design Automation Conference (DAC). 112--115."},{"key":"e_1_2_1_44_1","first-page":"1107","article-title":"SALSA: A new approach to scheduling with timing constraints","volume":"12","author":"Nestor J.","year":"1993","unstructured":"Nestor , J. and Krishnamoorthy , G. 1993 . SALSA: A new approach to scheduling with timing constraints . In IEEE Trans. CAD\/ICAS 12 , 8, 1107 -- 1122 . Nestor, J. and Krishnamoorthy, G. 1993. SALSA: A new approach to scheduling with timing constraints. In IEEE Trans. CAD\/ICAS 12, 8, 1107--1122.","journal-title":"IEEE Trans. CAD\/ICAS"},{"volume-title":"Proceedings of the IEEE International Symposiums on System Synthesis ISSS","author":"Nicolescu G.","key":"e_1_2_1_45_1","unstructured":"Nicolescu , G. , Yoo , S. , Bouchima , A. , and Jerraya , A. A . 2002. Validation in a component-based design flow for multicore SoCs . In Proceedings of the IEEE International Symposiums on System Synthesis ISSS . Kyoto, Japan. 10.1145\/581199.581236 Nicolescu, G., Yoo, S., Bouchima, A., and Jerraya, A. A. 2002. Validation in a component-based design flow for multicore SoCs. In Proceedings of the IEEE International Symposiums on System Synthesis ISSS. Kyoto, Japan. 10.1145\/581199.581236"},{"key":"e_1_2_1_46_1","volume-title":"Proceedings of the IEEE International Design Automation Conference (DAC). 10","author":"Note S.","year":"1991","unstructured":"Note , S. , Geurts , W. , Catthoor , F. , and De Man , H. 1991 . Cathedral-III: Architecture-driven high-level synthesis for high throughput DSP applications . In Proceedings of the IEEE International Design Automation Conference (DAC). 10 .1145\/127601.127739 Note, S., Geurts, W., Catthoor, F., and De Man, H. 1991. Cathedral-III: Architecture-driven high-level synthesis for high throughput DSP applications. In Proceedings of the IEEE International Design Automation Conference (DAC). 10.1145\/127601.127739"},{"key":"e_1_2_1_47_1","unstructured":"OCP-IP International Partnership. 2003. Open Core Protocol Specification v-2.0 http:\/\/www.ocpip.org.  OCP-IP International Partnership. 2003. Open Core Protocol Specification v-2.0 http:\/\/www.ocpip.org."},{"key":"e_1_2_1_48_1","unstructured":"Open System C Initiative (OSCI). 2001. SystemC Version 2.0 User's Guide Technical Report.  Open System C Initiative (OSCI). 2001. SystemC Version 2.0 User's Guide Technical Report."},{"volume-title":"Proceedings of the IEEE International Design Automation Conference (DAC). 10","author":"Passerone R.","key":"e_1_2_1_49_1","unstructured":"Passerone , R. and Rowson , J. A . 1998. Automatic synthesis of interfaces between incompatible protocols . In Proceedings of the IEEE International Design Automation Conference (DAC). 10 .1145\/277044.277047 Passerone, R. and Rowson, J. A. 1998. Automatic synthesis of interfaces between incompatible protocols. In Proceedings of the IEEE International Design Automation Conference (DAC). 10.1145\/277044.277047"},{"volume-title":"Proceedings of the IEEE International Design Automation Conference (DAC). 178--183","author":"Rowson J.","key":"e_1_2_1_50_1","unstructured":"Rowson , J. and Sangiovanni-Vincentelli , A . 1997. Interface-based design . In Proceedings of the IEEE International Design Automation Conference (DAC). 178--183 . 10.1145\/266021.266060 Rowson, J. and Sangiovanni-Vincentelli, A. 1997. Interface-based design. In Proceedings of the IEEE International Design Automation Conference (DAC). 178--183. 10.1145\/266021.266060"},{"volume-title":"Proceedings of Forum on Design Languages (FDL)","author":"Savaton G.","key":"e_1_2_1_51_1","unstructured":"Savaton , G. , Coussy , P. , Casseau , E. , and Martin , E . 2001. A methodology for behavioral virtual component specification targeting SoC design with high-level synthesis tools . In Proceedings of Forum on Design Languages (FDL) . Lyon, France. Savaton, G., Coussy, P., Casseau, E., and Martin, E. 2001. A methodology for behavioral virtual component specification targeting SoC design with high-level synthesis tools. In Proceedings of Forum on Design Languages (FDL). Lyon, France."},{"volume-title":"Proceedings of the IEEE International Design Automation Conference (DAC). 10","author":"Smith J.","key":"e_1_2_1_52_1","unstructured":"Smith , J. and De Micheli, G. 1998. Automated composition of hard-ware components . In Proceedings of the IEEE International Design Automation Conference (DAC). 10 .1145\/277044.277048 Smith, J. and De Micheli, G. 1998. Automated composition of hard-ware components. In Proceedings of the IEEE International Design Automation Conference (DAC). 10.1145\/277044.277048"},{"volume-title":"Proceedings of the IEEE International Design Automation Conference (DAC).","author":"Stoll A.","key":"e_1_2_1_53_1","unstructured":"Stoll , A. and Duzy , P . 1992. High-level synthesis from VHDL with exact timing constraints . In Proceedings of the IEEE International Design Automation Conference (DAC). Stoll, A. and Duzy, P. 1992. High-level synthesis from VHDL with exact timing constraints. In Proceedings of the IEEE International Design Automation Conference (DAC)."},{"volume-title":"Proceeding of IEEE 13th International Conference on Aplication-specific Systems, Architectures and Processors (ASAP).","author":"Turjan A.","key":"e_1_2_1_54_1","unstructured":"Turjan , A. , Kienhuis , B. , and Deprettere , E . 2002. A compile time based approach for solving out-of-order communication in Kahn Process Networks . In Proceeding of IEEE 13th International Conference on Aplication-specific Systems, Architectures and Processors (ASAP). Turjan, A., Kienhuis, B., and Deprettere, E. 2002. A compile time based approach for solving out-of-order communication in Kahn Process Networks. In Proceeding of IEEE 13th International Conference on Aplication-specific Systems, Architectures and Processors (ASAP)."},{"key":"e_1_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.831440"},{"key":"e_1_2_1_56_1","unstructured":"Virtual Socket Interface Alliance. 2000. VSI Alliance#8482; Virtual Component Interface Standard (OCB2 2.0) On-Chip Bus Development Working Group August.  Virtual Socket Interface Alliance. 2000. VSI Alliance#8482; Virtual Component Interface Standard (OCB2 2.0) On-Chip Bus Development Working Group August."},{"key":"e_1_2_1_57_1","unstructured":"Virtual Socket Interface Alliance. 2003. http:\/\/www.vsi.org.  Virtual Socket Interface Alliance. 2003. http:\/\/www.vsi.org."},{"key":"e_1_2_1_58_1","volume-title":"Proceedings of the IEEE International Design Automation Conference (DAC). 10","author":"Walkup E. A.","year":"1962","unstructured":"Walkup , E. A. and Borriello , G . 1994. Interface timing verification with application to synthesis . In Proceedings of the IEEE International Design Automation Conference (DAC). 10 .1145\/ 1962 44.196297 Walkup, E. A. and Borriello, G. 1994. Interface timing verification with application to synthesis. In Proceedings of the IEEE International Design Automation Conference (DAC). 10.1145\/196244.196297"},{"key":"e_1_2_1_59_1","doi-asserted-by":"crossref","unstructured":"Yen T. and Wolf W. 1996. Hardware-Software Co-Synthesis of Distributed Embedded Systems. Kluwer Academic Publ. Boston MA.   Yen T. and Wolf W. 1996. Hardware-Software Co-Synthesis of Distributed Embedded Systems. Kluwer Academic Publ. Boston MA.","DOI":"10.1007\/978-1-4757-5388-2"},{"volume-title":"Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD).","author":"Yen T.","key":"e_1_2_1_60_1","unstructured":"Yen , T. and Wolf , W . 1995. Communication synthesis for distributed embedded systems . In Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD). Yen, T. and Wolf, W. 1995. Communication synthesis for distributed embedded systems. In Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD)."},{"key":"e_1_2_1_61_1","unstructured":"Zissulescu-Ianculescu C. Turjan A. Kienhuis B. and Deprettere E. 2002. Solving out of order communication using CAM memory: An implementation. In ProRisc02 Veldhoven The Netherland.  Zissulescu-Ianculescu C. Turjan A. Kienhuis B. and Deprettere E. 2002. Solving out of order communication using CAM memory: An implementation. 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