{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:39:46Z","timestamp":1750307986914,"version":"3.41.0"},"reference-count":21,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2006,4,1]],"date-time":"2006-04-01T00:00:00Z","timestamp":1143849600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2006,4]]},"abstract":"<jats:p>New three-dimensional (3D) floorplanning and thermal via planning algorithms are proposed for thermal optimization in two-stacked die integration. Our contributions include (1) a two-stage design flow for 3D floorplanning, which scales down the enlarged solution space due to multidevice layer structure; (2) an efficient thermal-driven 3D floorplanning algorithm with power distribution constraints; (3) a thermal via planning algorithm considering congestion minimization. Experiments results show that our approach is nine times faster with better solution quality compared to a recent published result. In addition, the thermal via planning approach is proven to be very efficient to eliminate localized hot spots directly.<\/jats:p>","DOI":"10.1145\/1142155.1142159","type":"journal-article","created":{"date-parts":[[2006,7,25]],"date-time":"2006-07-25T14:14:26Z","timestamp":1153836866000},"page":"325-345","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":16,"title":["Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration"],"prefix":"10.1145","volume":"11","author":[{"given":"Zuoyuan","family":"Li","sequence":"first","affiliation":[{"name":"Tsinghua University, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xianlong","family":"Hong","sequence":"additional","affiliation":[{"name":"Tsinghua University, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Qiang","family":"Zhou","sequence":"additional","affiliation":[{"name":"Tsinghua University, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jinian","family":"Bian","sequence":"additional","affiliation":[{"name":"Tsinghua University, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hannah H.","family":"Yang","sequence":"additional","affiliation":[{"name":"Intel, USA, Hillsboro, OR"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vijay","family":"Pitchumani","sequence":"additional","affiliation":[{"name":"Intel, USA, Hillsboro, OR"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2006,4]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/96.659500"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.929647"},{"volume-title":"Proceedings of the 10th IEEE International Workshop on Rapid System Prototyping. 38--43","author":"Bazargan K.","key":"e_1_2_1_3_1","unstructured":"Bazargan , K. , Kastner , R. , and Sarrafzadeh , M . 1999. 3D floorplanning: Simulated annealing and greedy placement methods for reconfigurable computing systems . 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