{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,1]],"date-time":"2026-04-01T20:01:58Z","timestamp":1775073718796,"version":"3.50.1"},"reference-count":28,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2006,4,1]],"date-time":"2006-04-01T00:00:00Z","timestamp":1143849600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2006,4]]},"abstract":"<jats:p>A wide range of fault tolerance methods for FPGAs have been proposed. Approaches range from simple architectural redundancy to fully on-line adaptive implementations. The applications of these methods also differ; some are used only for manufacturing yield enhancement, while others can be used in-system. This survey attempts to provide an overview of the current state of the art for fault tolerance in FPGAs. It is assumed that faults have been previously detected and diagnosed; the methods presented are targeted towards tolerating the faults. A detailed description of each method is presented. Where applicable, the methods are compared using common metrics. Results are summarized to present a succinct, comprehensive comparison of the different approaches.<\/jats:p>","DOI":"10.1145\/1142155.1142167","type":"journal-article","created":{"date-parts":[[2006,7,25]],"date-time":"2006-07-25T14:14:26Z","timestamp":1153836866000},"page":"501-533","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":81,"title":["A survey of fault tolerant methodologies for FPGAs"],"prefix":"10.1145","volume":"11","author":[{"given":"Jason A.","family":"Cheatham","sequence":"first","affiliation":[{"name":"Wright State University, Dayton, OH"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"John M.","family":"Emmert","sequence":"additional","affiliation":[{"name":"Wright State University, Dayton, OH"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stan","family":"Baumgart","sequence":"additional","affiliation":[{"name":"University of North Carolina, Charlotte, Lexington, KY"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2006,4]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.67329"},{"key":"e_1_2_1_2_1","article-title":"Defect and fault tolerance SRAM-based FPGAs by shifting the configuration data. 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Partial reconfiguration of FPGA mapped designs with applications for fault tolerance and yield enhancement . In Proceedings of the 7th International Workshop on Field Programmable Logic and Applications. 141--150 . Emmert, J. M. and Bhatia, D. K. 1997. Partial reconfiguration of FPGA mapped designs with applications for fault tolerance and yield enhancement. In Proceedings of the 7th International Workshop on Field Programmable Logic and Applications. 141--150."},{"key":"e_1_2_1_6_1","volume-title":"Proceedings of the 11th Annual IEEE International ASIC Conference. IEEE Computer Society Press","author":"Emmert J.","unstructured":"Emmert , J. and Bhatia , D . 1998. Incremental routing in FPGAs . In Proceedings of the 11th Annual IEEE International ASIC Conference. IEEE Computer Society Press , Los Alamitos, CA, 217--221. Emmert, J. and Bhatia, D. 1998. Incremental routing in FPGAs. In Proceedings of the 11th Annual IEEE International ASIC Conference. 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Design methodologies for tolerating cell and interconnect faults in FPGAs. In International Conference on Computer Design. 326--331."},{"key":"e_1_2_1_11_1","volume-title":"Proceedings of the 9th International Conference on VLSI Design. 225--229","author":"Hanchek F.","unstructured":"Hanchek , F. and Dutt , S . 1996b. Node-covering based defect and fault tolerance methods for increased yield in FPGAs . In Proceedings of the 9th International Conference on VLSI Design. 225--229 . Hanchek, F. and Dutt, S. 1996b. Node-covering based defect and fault tolerance methods for increased yield in FPGAs. In Proceedings of the 9th International Conference on VLSI Design. 225--229."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.656073"},{"key":"e_1_2_1_13_1","volume-title":"Proceedings of the IEEE Custom Integrated Circuits Conference. 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An approach for the yield enhancement of programmable gate arrays . In Proceedings of the IEEE\/ACM International Conference on Computer Aided Design. ACM , New York, 226--229. Kumar, V., Dahbura, A., Fischer, F., and Juola, P. 1989. An approach for the yield enhancement of programmable gate arrays. In Proceedings of the IEEE\/ACM International Conference on Computer Aided Design. ACM, New York, 226--229."},{"key":"e_1_2_1_17_1","volume-title":"Proceedings of the 25th ACM\/IEEE Design Automation Conference. ACM","author":"Kuo S.-Y.","unstructured":"Kuo , S.-Y. and Fuchs , W. K . 1988. Spare allocation and reconfiguration in large area VLSI . In Proceedings of the 25th ACM\/IEEE Design Automation Conference. ACM , New York, 609--612. Kuo, S.-Y. and Fuchs, W. K. 1988. Spare allocation and reconfiguration in large area VLSI. In Proceedings of the 25th ACM\/IEEE Design Automation Conference. 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