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At the same time, the applications that need to run on such platforms have become increasingly complex and have tight power and performance requirements. Achieving a satisfactory design quality under these circumstances is only possible when both computation and communication refinement are performed efficiently, in an automated and synergistic manner. Consequently, formal and disciplined system-level design methodologies are in great demand for future multiprocessor design. This article provides a broad overview of some fundamental research issues and state-of-the-art solutions concerning both computation and communication aspects of system-level design. The methodology we advocate consists of developing abstract application and platform models, followed by application mapping onto the target platform, and then optimizing the overall system via performance analysis. In addition, a communication refinement step is critical for optimizing the communication infrastructure in this multiprocessor setup. Finally, simulation and prototyping can be used for accurate performance evaluation purposes.<\/jats:p>","DOI":"10.1145\/1142980.1142983","type":"journal-article","created":{"date-parts":[[2006,7,25]],"date-time":"2006-07-25T14:14:26Z","timestamp":1153836866000},"page":"564-592","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":17,"title":["Computation and communication refinement for multiprocessor SoC design"],"prefix":"10.1145","volume":"11","author":[{"given":"Radu","family":"Marculescu","sequence":"first","affiliation":[{"name":"Carnegie Mellon University, Pittsburgh, PA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Umit Y.","family":"Ogras","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University, Pittsburgh, PA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nicholas H.","family":"Zamora","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University, Pittsburgh, PA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2004,6,7]]},"reference":[{"volume-title":"Proceedings of the Design Automation and Test in Europe Conference.","author":"Adriahantenaina A.","key":"e_1_2_1_1_1","unstructured":"Adriahantenaina , A. and Greiner , A . 2003. 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A., Mignolet, J.-Y., Nollet, V., Marescaux, T., Verkest, D., Vernalde, S., and Lauwereins, R. 2003. Highly scalable network on chip for reconfigurable systems. In Proceedings of the International Symposium on System-on-Chip."},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"volume-title":"Statistics for Long-Memory Processes","author":"Beran J.","key":"e_1_2_1_7_1","unstructured":"Beran , J. 1994. Statistics for Long-Memory Processes . Chapman & Hall , London . Beran, J. 1994. Statistics for Long-Memory Processes. Chapman & Hall, London."},{"key":"e_1_2_1_8_1","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1016\/0304-3975(85)90088-X","article-title":"Algebra of communicating processes with abstraction","volume":"37","author":"Bergstra J. A.","year":"1985","unstructured":"Bergstra , J. A. and Klop , J. W. 1985 . Algebra of communicating processes with abstraction . Theoretical Comput. Sci. 37 , 1 . Bergstra, J. A. and Klop, J. W. 1985. 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Prentice-Hall Upper Saddle River N.J."},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.1044297"},{"volume-title":"Proceedings of the Design Automation and Test in Europe Conference.","author":"Chandra V.","key":"e_1_2_1_12_1","unstructured":"Chandra , V. , Xu , A. , Schmit , H. , and Pileggi , L . 2004. An interconnect channel design for high performance integrated circuits . In Proceedings of the Design Automation and Test in Europe Conference. Chandra, V., Xu, A., Schmit, H., and Pileggi, L. 2004. An interconnect channel design for high performance integrated circuits. In Proceedings of the Design Automation and Test in Europe Conference."},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/71.877831"},{"key":"e_1_2_1_14_1","volume-title":"Proceedings of the Pacific Rim International Symposium on Dependable Computing.","author":"Constantinescu C.","year":"2001","unstructured":"Constantinescu , C. 2001 . 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IBM CoreConnect. 2006. http:\/\/www.chips.ibm.com\/products\/powerpc\/cores."},{"key":"e_1_2_1_35_1","volume-title":"Proceedings of the Design Automation and Test in Europe Conference.","author":"Jalabert A.","year":"2004","unstructured":"Jalabert , A. , Murali , S. , Benini , L. , and De Micheli , G. 2004 . \u00d7 pipesCompiler: A tool for instantiating application specific networks on chip . In Proceedings of the Design Automation and Test in Europe Conference. Jalabert, A., Murali, S., Benini, L., and De Micheli, G. 2004. \u00d7 pipesCompiler: A tool for instantiating application specific networks on chip. In Proceedings of the Design Automation and Test in Europe Conference."},{"key":"e_1_2_1_36_1","volume-title":"(Eds.)","author":"Jantsch A.","year":"2003","unstructured":"Jantsch , A. and Tenhunen , H . (Eds.) . 2003 . Networks-on-Chip. Kluwer , Hingham, Mass. Jantsch, A. and Tenhunen, H. (Eds.). 2003. Networks-on-Chip. Kluwer, Hingham, Mass."},{"volume-title":"The semantics of a simple language for parallel programming","author":"Kahn G.","key":"e_1_2_1_37_1","unstructured":"Kahn , G. 1974. The semantics of a simple language for parallel programming . In Information Processing, J. L. Rosenfeld, ed. Stockholm, Sweden . Kahn, G.1974. The semantics of a simple language for parallel programming. In Information Processing, J. L. Rosenfeld, ed. Stockholm, Sweden."},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.509908"},{"key":"e_1_2_1_39_1","doi-asserted-by":"crossref","first-page":"1235","DOI":"10.1109\/PROC.1987.13876","article-title":"Synchronous dataflow","volume":"75","author":"Lee E.","year":"1987","unstructured":"Lee , E. and Messerschmitt , D. 1987 . Synchronous dataflow . In Proc. IEEE 75 , 9, 1235 -- 1245 . Lee, E. and Messerschmitt, D. 1987. Synchronous dataflow. In Proc. IEEE 75, 9, 1235--1245.","journal-title":"Proc. IEEE"},{"key":"e_1_2_1_40_1","first-page":"5","article-title":"Dataflow process networks","volume":"83","author":"Lee E.","year":"1995","unstructured":"Lee , E. and Parks , T. M. 1995 . Dataflow process networks . Proc. IEEE 83 , 5 . Lee, E. and Parks, T. M. 1995. Dataflow process networks. Proc. IEEE 83, 5.","journal-title":"Proc. IEEE"},{"volume-title":"Proceedings of the Design Automation Conference. 10","author":"Lee H. G.","key":"e_1_2_1_41_1","unstructured":"Lee , H. G. , Ogras , U. Y. , Marculescu , R. , and Chang , N . 2006. Design space exploration and prototyping for on-chip multimedia applications . In Proceedings of the Design Automation Conference. 10 .1145\/1146909.1146949 Lee, H. G., Ogras, U. Y., Marculescu, R., and Chang, N. 2006. Design space exploration and prototyping for on-chip multimedia applications. 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System-Level power\/performance analysis of portable multimedia systems communicating over wireless channels . In Proceedings of the IEEE\/ACM International Conference on Computer Aided Design. Marculescu, R., Nandi, A., Lavagno, L., and Sangiovanni-Vincentelli, A. 2001. System-Level power\/performance analysis of portable multimedia systems communicating over wireless channels. In Proceedings of the IEEE\/ACM International Conference on Computer Aided Design."},{"volume-title":"Proceedings of the Asia and South Pacific Design Automation Conference.","author":"Maxiaguine A.","key":"e_1_2_1_47_1","unstructured":"Maxiaguine , A. , Kuenzli , S. , Chakraborty S. , and Thiele , L . 2004. Rate analysis for streaming applications with on-chip buffer constraints . In Proceedings of the Asia and South Pacific Design Automation Conference. Maxiaguine, A., Kuenzli, S., Chakraborty S., and Thiele, L. 2004. Rate analysis for streaming applications with on-chip buffer constraints. In Proceedings of the Asia and South Pacific Design Automation Conference."},{"volume-title":"Communication and Concurrency","author":"Milner R.","key":"e_1_2_1_48_1","unstructured":"Milner , R. 1989. Communication and Concurrency . Prentice-Hall , Englewood Cliffs, N.J. Milner, R. 1989. Communication and Concurrency. Prentice-Hall, Englewood Cliffs, N.J."},{"key":"e_1_2_1_49_1","doi-asserted-by":"crossref","unstructured":"Mishra P. Shrivastava A. and Dutt N. Architecture description language (ADL-) Driven software toolkit generation for architectural exploration of programmable SOCs. ACM Trans. Design Autom. Elect. Syst. 11 3 626--658. 10.1145\/1142980.1142985   Mishra P. Shrivastava A. and Dutt N. Architecture description language (ADL-) Driven software toolkit generation for architectural exploration of programmable SOCs. ACM Trans. Design Autom. Elect. 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In Proceedings of the Design Automation and Test in Europe Conference."},{"volume-title":"Proceedings of the Design Automation Conference. 10","author":"Murali S.","key":"e_1_2_1_52_1","unstructured":"Murali , S. and De Micheli, G. 2004b. SUNMAP: A tool for automatic topology selection and generation for NoCs . In Proceedings of the Design Automation Conference. 10 .1145\/996566.996809 Murali, S. and De Micheli, G. 2004b. SUNMAP: A tool for automatic topology selection and generation for NoCs. In Proceedings of the Design Automation Conference. 10.1145\/996566.996809"},{"volume-title":"Proceedings of the 38th ACM\/IEEE Design Automation Conference. 10","author":"Nandi A.","key":"e_1_2_1_53_1","unstructured":"Nandi , A. and Marculescu , R . 2001. System-Level power\/performance analysis for embedded systems design . In Proceedings of the 38th ACM\/IEEE Design Automation Conference. 10 .1145\/378239.379032 Nandi, A. and Marculescu, R. 2001. System-Level power\/performance analysis for embedded systems design. In Proceedings of the 38th ACM\/IEEE Design Automation Conference. 10.1145\/378239.379032"},{"key":"e_1_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.191995"},{"key":"e_1_2_1_55_1","doi-asserted-by":"crossref","first-page":"3","DOI":"10.1007\/BF01158964","article-title":"A storage model with self-similar input","volume":"16","author":"Norros I.","year":"1994","unstructured":"Norros , I. 1994 . A storage model with self-similar input . Queueing Syst. 16 , 3 -- 4 , 387--396. Norros, I. 1994. A storage model with self-similar input. Queueing Syst. 16, 3--4, 387--396.","journal-title":"Queueing Syst."},{"volume-title":"Proceedings of the 3rd IEEE\/ACM\/IFIP International Conference on Hardware\/Software Codesign and System Synthses. 10","author":"Ogras U. Y.","key":"e_1_2_1_56_1","unstructured":"Ogras , U. Y. , Hu , J. , and Marculescu , R . 2005. Key research problems in NoC design: A holistic perspective . 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Fault tolerant algorithms for network-on-chip interconnect. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI."},{"key":"e_1_2_1_66_1","doi-asserted-by":"publisher","DOI":"10.1109\/32.99196"},{"key":"e_1_2_1_67_1","doi-asserted-by":"publisher","DOI":"10.1016\/0743-7315(91)90007-V"},{"key":"e_1_2_1_68_1","doi-asserted-by":"publisher","DOI":"10.1145\/1142980.1142984"},{"volume-title":"Proceedings of the International Symposium on Circuits and Systems.","author":"Saastamoinen I.","key":"e_1_2_1_69_1","unstructured":"Saastamoinen , I. , Alho , M. , and Nurmi , J . 2003. Buffer implementation for proteo network-on-chip . In Proceedings of the International Symposium on Circuits and Systems. Saastamoinen, I., Alho, M., and Nurmi, J. 2003. Buffer implementation for proteo network-on-chip. In Proceedings of the International Symposium on Circuits and Systems."},{"key":"e_1_2_1_70_1","unstructured":"Semiconductor Association. 2003. The International Technology Roadmap for Semiconductors (ITRS).  Semiconductor Association. 2003. The International Technology Roadmap for Semiconductors (ITRS)."},{"key":"e_1_2_1_71_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.852438"},{"volume-title":"Proceedings of the IEEE International Conference on Computer Design.","author":"Srinivasan K.","key":"e_1_2_1_72_1","unstructured":"Srinivasan , K. , Chatha , K. S. , and Konjevod , G . 2004. Linear programming based techniques for synthesis of network-on-chip architectures . In Proceedings of the IEEE International Conference on Computer Design. Srinivasan, K., Chatha, K. S., and Konjevod, G. 2004. Linear programming based techniques for synthesis of network-on-chip architectures. In Proceedings of the IEEE International Conference on Computer Design."},{"key":"e_1_2_1_73_1","unstructured":"Sriram S. and Bhattacharyya S. S. 2001. Embedded Multiprocessors Scheduling and Synchronization. Marcel Dekker New York.   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