{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T04:01:22Z","timestamp":1725768082612},"publisher-location":"New York, NY, USA","reference-count":10,"publisher":"ACM","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2006,8,28]]},"DOI":"10.1145\/1150343.1150350","type":"proceedings-article","created":{"date-parts":[[2006,10,18]],"date-time":"2006-10-18T18:04:00Z","timestamp":1161194640000},"page":"1-4","update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":16,"title":["Exploiting dynamic and partial reconfiguration for FPGAs"],"prefix":"10.1145","author":[{"given":"M.","family":"H\u00fcbner","sequence":"first","affiliation":[{"name":"Universit\u00e4t Karlsruhe (TH), Germany"}]},{"given":"J.","family":"Becker","sequence":"additional","affiliation":[{"name":"Universit\u00e4t Karlsruhe (TH), Germany"}]}],"member":"320","published-online":{"date-parts":[[2006,8,28]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"J. Becker M. H\u00fcbner M. Ullmann: \"Real-Time Dynamically Run-Time Reconfiguration for Power-\/Cost-optimized Virtex FPGA Realizations\" VLSI03 Darmstadt Sep. 03  J. Becker M. H\u00fcbner M. Ullmann: \"Real-Time Dynamically Run-Time Reconfiguration for Power-\/Cost-optimized Virtex FPGA Realizations\" VLSI03 Darmstadt Sep. 03"},{"key":"e_1_3_2_1_2_1","unstructured":"M. Ullmann M. Huebner B. Grimm J. Becker: \"An FPGA Run-Time System for Dynamical On-Demand Reconfiguration\" RAW04 Santa Fee  M. Ullmann M. Huebner B. Grimm J. Becker: \"An FPGA Run-Time System for Dynamical On-Demand Reconfiguration\" RAW04 Santa Fee"},{"key":"e_1_3_2_1_3_1","unstructured":"J. Becker M. H\u00fcbner M. Ullmann: \"Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-offs and Limitations\" SBCCI03 Sao Paulo Sep. 03   J. Becker M. H\u00fcbner M. Ullmann: \"Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-offs and Limitations\" SBCCI03 Sao Paulo Sep. 03"},{"key":"e_1_3_2_1_4_1","unstructured":"L. Benini G. De Micheli: \"Networks on Chip: A New Paradigm for Systems on Chip Design\" Date 02 March 3-7 Paris France   L. Benini G. De Micheli: \"Networks on Chip: A New Paradigm for Systems on Chip Design\" Date 02 March 3-7 Paris France"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1016568.1016583"},{"key":"e_1_3_2_1_6_1","unstructured":"XAPP291 Xilinx Application note  XAPP291 Xilinx Application note"},{"key":"e_1_3_2_1_7_1","unstructured":"J. C. Palma A. Vieira de Melo F. G. Moraes N. Calazans \"Core Communication Interface for FPGAs\" SBCCI02 Porto Alegre BRAZIL   J. C. Palma A. Vieira de Melo F. G. Moraes N. Calazans \"Core Communication Interface for FPGAs\" SBCCI02 Porto Alegre BRAZIL"},{"key":"e_1_3_2_1_8_1","unstructured":"M. H\u00fcbner K. Paulsson M. Stitz J. Becker: \"Novel Seamless Design-Flow for Partial and Dynamic Reconfigurable Systems with Customized Communication Structures Based on Xilinx Virtex-II FPGAs\" ARCS05 Innsbruck Austria  M. H\u00fcbner K. Paulsson M. Stitz J. Becker: \"Novel Seamless Design-Flow for Partial and Dynamic Reconfigurable Systems with Customized Communication Structures Based on Xilinx Virtex-II FPGAs\" ARCS05 Innsbruck Austria"},{"key":"e_1_3_2_1_9_1","unstructured":"B. Blodget C. Bobda M. Huebner A. Niyonkuru: \"Partial and Dynamically Reconfiguration of Xilinx Virtex-II FPGAs\" FPL04 Antwerp Belgium  B. Blodget C. Bobda M. Huebner A. Niyonkuru: \"Partial and Dynamically Reconfiguration of Xilinx Virtex-II FPGAs\" FPL04 Antwerp Belgium"},{"key":"e_1_3_2_1_10_1","unstructured":"B. Blodget S. McMillan: \"A lightweight approach for embedded reconfiguration of FPGAs\" Date03 Munich Germany   B. Blodget S. McMillan: \"A lightweight approach for embedded reconfiguration of FPGAs\" Date03 Munich Germany"}],"event":{"name":"SBCCI06: 19th Symposium on Integrated Circuits and System Design","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"],"location":"Ouro Preto MG Brazil","acronym":"SBCCI06"},"container-title":["Proceedings of the 19th annual symposium on Integrated circuits and systems design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1150343.1150350","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,7]],"date-time":"2023-01-07T20:47:54Z","timestamp":1673124474000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1150343.1150350"}},"subtitle":["toolflow, architecture and system integration"],"short-title":[],"issued":{"date-parts":[[2006,8,28]]},"references-count":10,"alternative-id":["10.1145\/1150343.1150350","10.1145\/1150343"],"URL":"https:\/\/doi.org\/10.1145\/1150343.1150350","relation":{},"subject":[],"published":{"date-parts":[[2006,8,28]]},"assertion":[{"value":"2006-08-28","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}