{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T10:30:47Z","timestamp":1761647447975},"reference-count":44,"publisher":"Association for Computing Machinery (ACM)","issue":"2","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2006,5]]},"abstract":"<jats:p>With the help of HW\/SW codesign, system-on-chip (SoC) can effectively reduce cost, improve reliability, and produce versatile products. The growing complexity of SoC designs makes on-chip communication subsystem design as important as computation subsystem design. While a number of codesign methodologies have been proposed for on-chip computation subsystems, many works are needed for on-chip communication subsystems. This paper proposes application-specific networks-on-chip (ASNoC) and its design methodology. ASNoC is used for two high-performance SoC applications. The methodology (1) can automatically generate optimized ASNoC for different applications, (2) can generate a corresponding distributed shared memory along with an ASNoC, (3) can use both recorded and statistical communication traces for cycle-accurate performance analysis, (4) is based on standardized network component library and floorplan to estimate power and area, (5) adapts an industrial-grade network modeling and simulation environment, OPNET, which makes the methodology ready to use, and (6) can be easily integrated into current HW\/SW codesign flow. Using the methodology, ASNoC is generated for a H.264 HDTV decoder SoC and Smart Camera SoC. ASNoC and 2D mesh networks-on-chip are compared in performance, power, and area in detail. The comparison results show that ASNoC provide substantial improvements in power, performance, and cost compared to 2D mesh networks-on-chip. In the H.264 HDTV decoder SoC, ASNoC uses 39% less power, 59% less silicon area, 74% less metal area, 63% less switch capacity, and 69% less interconnection capacity to achieve 2X performance compared to 2D mesh networks-on-chip.<\/jats:p>","DOI":"10.1145\/1151074.1151076","type":"journal-article","created":{"date-parts":[[2006,10,18]],"date-time":"2006-10-18T18:11:32Z","timestamp":1161195092000},"page":"263-280","update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":72,"title":["A design methodology for application-specific networks-on-chip"],"prefix":"10.1145","volume":"5","author":[{"given":"Jiang","family":"Xu","sequence":"first","affiliation":[{"name":"Princeton University, Princeton, NJ"}]},{"given":"Wayne","family":"Wolf","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ"}]},{"given":"Joerg","family":"Henkel","sequence":"additional","affiliation":[{"name":"University of Karlsruhe, Germany"}]},{"given":"Srimat","family":"Chakradhar","sequence":"additional","affiliation":[{"name":"NEC Laboratories America, Inc., Princeton, NJ"}]}],"member":"320","published-online":{"date-parts":[[2006,5]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Automation and Test in Europe Conference and Exhibition.","author":"Adriahantenaina A.","unstructured":"Adriahantenaina , A. , Charlery , H. , Greiner , A. , Mortiez , L. , and Zeferino , C. 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