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The design flow tools are governed in a single framework that combines the subtools into a seamless flow and visualizes the design process. Novel features also include an automated architecture exploration based on the system models in UML, as well as the automatic back and forward annotation of information in the design flow. The architecture exploration is based on the global optimization of systems that are composed of subsystems, which are then locally optimized for their particular purposes. As a result, the design flow produces an optimized component allocation, task mapping, and scheduling for the described application. In addition, it implements the entire system for FPGA prototyping board. As a case study, the design flow is utilized in the integration of state-of-the-art technology approaches, including a wireless terminal architecture, a network-on-chip, and multiprocessing utilizing RTOS in a SoC. In this study, a central part of a WLAN terminal is modeled, verified, optimized, and prototyped with the presented framework.<\/jats:p>","DOI":"10.1145\/1151074.1151077","type":"journal-article","created":{"date-parts":[[2006,10,18]],"date-time":"2006-10-18T18:11:32Z","timestamp":1161195092000},"page":"281-320","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":124,"title":["UML-based multiprocessor SoC design framework"],"prefix":"10.1145","volume":"5","author":[{"given":"Tero","family":"Kangas","sequence":"first","affiliation":[{"name":"Tampere University of Technology, Tampere, Finland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Petri","family":"Kukkala","sequence":"additional","affiliation":[{"name":"Tampere University of Technology, Tampere, Finland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Heikki","family":"Orsila","sequence":"additional","affiliation":[{"name":"Tampere University of Technology, Tampere, Finland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Erno","family":"Salminen","sequence":"additional","affiliation":[{"name":"Tampere University of Technology, Tampere, Finland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marko","family":"H\u00e4nnik\u00e4inen","sequence":"additional","affiliation":[{"name":"Tampere University of Technology, Tampere, Finland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Timo D.","family":"H\u00e4m\u00e4l\u00e4inen","sequence":"additional","affiliation":[{"name":"Tampere University of Technology, Tampere, Finland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jouni","family":"Riihim\u00e4ki","sequence":"additional","affiliation":[{"name":"Nokia Technology Platforms, Tampere, Finland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kimmo","family":"Kuusilinna","sequence":"additional","affiliation":[{"name":"Nokia Research Center, Tampere, Finland"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2006,5]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"Altera Homepage. 2005. http:\/\/www.altera.com.  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In Proceedings IEEE Computer Society Workshop On VLSI. 100--105."},{"key":"e_1_2_1_16_1","volume-title":"Proceedings of IFIP Congress 74","author":"Kahn G.","year":"1974","unstructured":"Kahn , G. 1974 . The semantics of a simple language for parallel programming . In Proceedings of IFIP Congress 74 . 471--475. Kahn, G. 1974. The semantics of a simple language for parallel programming. In Proceedings of IFIP Congress 74. 471--475."},{"key":"e_1_2_1_17_1","volume-title":"Proceedings of the International Symposium on System-on-Chip. 105--108","author":"Kangas T.","unstructured":"Kangas , T. , Riihim\u00e4ki , J. , Salminen , E. , Kuusilinna , K. , and H\u00e4m\u00e4l\u00e4inen , T . 2003. Using a communication generator in SoC architecture exploration . In Proceedings of the International Symposium on System-on-Chip. 105--108 . Kangas, T., Riihim\u00e4ki, J., Salminen, E., Kuusilinna, K., and H\u00e4m\u00e4l\u00e4inen, T. 2003. Using a communication generator in SoC architecture exploration. In Proceedings of the International Symposium on System-on-Chip. 105--108."},{"key":"e_1_2_1_18_1","doi-asserted-by":"crossref","unstructured":"Kienhuis B. Deprettere E. van der Wolf P. and Vissers K. 2002. A methodology to design programmable embedded systems---the Y-chart approach. In Lecture Notes in Computer Science. Vol. 2268. Springer-Verlag Berlin Germany 18--37.   Kienhuis B. Deprettere E. van der Wolf P. and Vissers K. 2002. A methodology to design programmable embedded systems---the Y-chart approach. In Lecture Notes in Computer Science. Vol. 2268. Springer-Verlag Berlin Germany 18--37.","DOI":"10.1007\/3-540-45874-3_2"},{"key":"e_1_2_1_19_1","doi-asserted-by":"crossref","unstructured":"Kirkpatrick S. Gelatt  Jr. C. and Vecchi M. 1983. Optimization by simulated annealing. Science 220 4598 671--680.  Kirkpatrick S. Gelatt Jr. C. and Vecchi M. 1983. Optimization by simulated annealing. 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Marcon, C., Hessel, F., Amory, A., Ries, L., Moraes, F., and Calazans, N. 2002. Prototyping of embedded digital systems from SDL language: A case study. In Proceedings of 7th IEEE International High-Level Design Validation and Test Workshop. 133--138."},{"key":"e_1_2_1_25_1","unstructured":"Mentor Graphics Homepage. 2005. http:\/\/www.mentor.com.  Mentor Graphics Homepage. 2005. http:\/\/www.mentor.com."},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/REAL.2004.32"},{"key":"e_1_2_1_27_1","unstructured":"Object Management Group (OMG). 2005. UML Profile for Schedulability Performance and Time Specification (Version 1.1).  Object Management Group (OMG). 2005. UML Profile for Schedulability Performance and Time Specification (Version 1.1)."},{"key":"e_1_2_1_28_1","volume-title":"Proceedings of the International Symposium on System-on-Chip. 146--150","author":"Orsila H.","unstructured":"Orsila , H. , Kangas , T. , and H\u00e4m\u00e4l\u00e4inen , T . 2005. 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International Journal of Embedded Systems 1, 7.","journal-title":"International Journal of Embedded Systems"},{"key":"e_1_2_1_30_1","unstructured":"Ptolemy Project. 2005. http:\/\/ptolemy.eecs.berkeley.edu.  Ptolemy Project. 2005. http:\/\/ptolemy.eecs.berkeley.edu."},{"key":"e_1_2_1_31_1","volume-title":"Proceedings of the IEEE International Symposium of Circuits and Systems. 61--64","author":"Riihim\u00e4ki J.","unstructured":"Riihim\u00e4ki , J. , Salminen , E. , Kuusilinna , K. , and H\u00e4m\u00e4l\u00e4inen , T . 2002. Parameter optimization tool for enhancing on-chip network performance . In Proceedings of the IEEE International Symposium of Circuits and Systems. 61--64 . Riihim\u00e4ki, J., Salminen, E., Kuusilinna, K., and H\u00e4m\u00e4l\u00e4inen, T. 2002. Parameter optimization tool for enhancing on-chip network performance. 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