{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:41:21Z","timestamp":1750308081125,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":22,"publisher":"ACM","license":[{"start":{"date-parts":[[2006,9,16]],"date-time":"2006-09-16T00:00:00Z","timestamp":1158364800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2006,9,16]]},"DOI":"10.1145\/1152154.1152168","type":"proceedings-article","created":{"date-parts":[[2006,10,18]],"date-time":"2006-10-18T22:04:00Z","timestamp":1161209040000},"page":"64-73","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":7,"title":["Self-checking instructions"],"prefix":"10.1145","author":[{"given":"Sumeet","family":"Kumar","sequence":"first","affiliation":[{"name":"Binghamton University, Binghamton, NY"}]},{"given":"Aneesh","family":"Aggarwal","sequence":"additional","affiliation":[{"name":"Binghamton University, Binghamton, NY"}]}],"member":"320","published-online":{"date-parts":[[2006,9,16]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.5555\/320080.320111"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/268806.268810"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605419"},{"key":"e_1_3_2_1_4_1","unstructured":"Compaq Computer Corp. \"Data integrity for Compaq Non-Stop Himalaya servers \" http:\/\/nonstop.compaq.com 1999.  Compaq Computer Corp. \"Data integrity for Compaq Non-Stop Himalaya servers \" http:\/\/nonstop.compaq.com 1999."},{"key":"e_1_3_2_1_5_1","volume-title":"ICPP-21","author":"Holm J. G.","year":"1992","unstructured":"J. G. Holm , and P. Banerjee , \" Low cost concurrent error detection in a VLIW architecture using replicated instructions\" Proc . ICPP-21 , 1992 . J. G. Holm, and P. Banerjee, \"Low cost concurrent error detection in a VLIW architecture using replicated instructions\" Proc. ICPP-21, 1992."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859631"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/277044.277226"},{"key":"e_1_3_2_1_8_1","volume-title":"Proc. HPCA","author":"Kumar S.","year":"2006","unstructured":"S. Kumar , et. al., \" Reducing Resource Redundancy for Concurrent Error Detection Techniques in High Performance Microprocessor ,\" Proc. HPCA , 2006 . S. Kumar, et. al., \"Reducing Resource Redundancy for Concurrent Error Detection Techniques in High Performance Microprocessor,\" Proc. HPCA, 2006."},{"key":"e_1_3_2_1_9_1","volume-title":"et. al., \"A Systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor,\" Micro-36","author":"Mukherjee S.","year":"2003","unstructured":"S. Mukherjee , et. al., \"A Systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor,\" Micro-36 , 2003 . S. Mukherjee, et. al., \"A Systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor,\" Micro-36, 2003."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1982.1676055"},{"key":"e_1_3_2_1_11_1","volume-title":"Micro-34","author":"Ray J.","year":"2001","unstructured":"J. Ray , J. Hoe , and B. Falsafi , \" Dual use of superscalar datapath for transient-fault detection and recovery,\" Proc . Micro-34 , 2001 . J. Ray, J. Hoe, and B. Falsafi, \"Dual use of superscalar datapath for transient-fault detection and recovery,\" Proc. Micro-34, 2001."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339652"},{"key":"e_1_3_2_1_13_1","volume-title":"Symp. on Fault-Tolerant Computing Systems","author":"Rotenberg E.","year":"1999","unstructured":"E. Rotenberg , \"AR-SMT : A microarchitectural approach to fault tolerance in microprocessors,\" Proc. of the 29th Intl . Symp. on Fault-Tolerant Computing Systems , June 1999 . E. Rotenberg, \"AR-SMT: A microarchitectural approach to fault tolerance in microprocessors,\" Proc. of the 29th Intl. Symp. on Fault-Tolerant Computing Systems, June 1999."},{"key":"e_1_3_2_1_15_1","volume-title":"Reliable Computer Systems Design and Evaluation,\" The Digital Press","author":"Siewiorek D. P.","year":"1992","unstructured":"D. P. Siewiorek and R. S. Swarz , \" Reliable Computer Systems Design and Evaluation,\" The Digital Press , 1992 . D. P. Siewiorek and R. S. Swarz, \"Reliable Computer Systems Design and Evaluation,\" The Digital Press, 1992."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.755464"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.19"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379247"},{"key":"e_1_3_2_1_19_1","volume-title":"ISCA-29","author":"Vijaykumar T.","year":"2002","unstructured":"T. Vijaykumar , I. Pomeranz , and K. Cheng , \" Transient-fault recovery using simultaneous multithreading,\" Proc . ISCA-29 , 2002 . T. Vijaykumar, I. Pomeranz, and K. Cheng, \"Transient-fault recovery using simultaneous multithreading,\" Proc. ISCA-29, 2002."},{"key":"e_1_3_2_1_20_1","volume-title":"ISCA-31","author":"Weaver C.","year":"2004","unstructured":"C. Weaver , et. al., \" Techniques to Reduce the Soft Error Rate of a High Performance Microprocessor,\" Proc . ISCA-31 , 2004 . C. Weaver, et. al., \"Techniques to Reduce the Soft Error Rate of a High Performance Microprocessor,\" Proc. ISCA-31, 2004."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.38"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.43"},{"key":"e_1_3_2_1_24_1","volume-title":"et. al, \"A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy\" ISCA-31","author":"Parashar A.","year":"2004","unstructured":"A. Parashar , et. al, \"A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy\" ISCA-31 , 2004 . A. Parashar, et. al, \"A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy\" ISCA-31, 2004."}],"event":{"name":"PACT06: 2006 International Conference on Parallel Architectures and Compilation Techniques","sponsor":["ACM Association for Computing Machinery"],"location":"Seattle Washington USA","acronym":"PACT06"},"container-title":["Proceedings of the 15th international conference on Parallel architectures and compilation techniques"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1152154.1152168","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1152154.1152168","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T16:07:43Z","timestamp":1750262863000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1152154.1152168"}},"subtitle":["reducing instruction redundancy for concurrent error detection"],"short-title":[],"issued":{"date-parts":[[2006,9,16]]},"references-count":22,"alternative-id":["10.1145\/1152154.1152168","10.1145\/1152154"],"URL":"https:\/\/doi.org\/10.1145\/1152154.1152168","relation":{},"subject":[],"published":{"date-parts":[[2006,9,16]]},"assertion":[{"value":"2006-09-16","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}