{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,16]],"date-time":"2026-07-16T06:18:48Z","timestamp":1784182728424,"version":"3.55.0"},"publisher-location":"New York, NY, USA","reference-count":44,"publisher":"ACM","license":[{"start":{"date-parts":[[2006,10,20]],"date-time":"2006-10-20T00:00:00Z","timestamp":1161302400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2006,10,20]]},"DOI":"10.1145\/1168857.1168878","type":"proceedings-article","created":{"date-parts":[[2007,1,16]],"date-time":"2007-01-16T20:15:56Z","timestamp":1168978556000},"page":"163-174","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":63,"title":["Tartan"],"prefix":"10.1145","author":[{"given":"Mahim","family":"Mishra","sequence":"first","affiliation":[{"name":"Carnegie Mellon University, Pittsburgh, PA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Timothy J.","family":"Callahan","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University, Pittsburgh, PA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Tiberiu","family":"Chelcea","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University, Pittsburgh, PA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Girish","family":"Venkataramani","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University, Pittsburgh, PA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Seth C.","family":"Goldstein","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University, Pittsburgh, PA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mihai","family":"Budiu","sequence":"additional","affiliation":[{"name":"Microsoft Research"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2006,10,20]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1016\/0743-7315(91)90016-3"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2005.7"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339657"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2005.1430572"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.5555\/647929.740544"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.5555\/795660.795951"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1024393.1024396"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/354880.354889"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1007512717742"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.831476"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/115372.115320"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008141305507"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.5555\/1129601.1129695"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/300979.300982"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.1994.303848"},{"key":"e_1_3_2_1_17_1","first-page":"280","article-title":"A defect-tolerant computer architecture: Opportunities for nanotechnology","author":"Heath J.R.","year":"1998","unstructured":"J.R. Heath , P.J. Kuekes , A defect-tolerant computer architecture: Opportunities for nanotechnology . Science , 280 , 1998 . J.R. Heath, P.J. Kuekes, et al. A defect-tolerant computer architecture: Opportunities for nanotechnology. Science, 280, 1998.","journal-title":"Science"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.159"},{"key":"e_1_3_2_1_19_1","volume-title":"January","author":"Intel Corp.","year":"2006","unstructured":"Intel Corp. Intel Pentium M Datasheet , January 2006 . Intel Corp. Intel Pentium M Datasheet, January 2006."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/774572.774593"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1117201.1117205"},{"key":"e_1_3_2_1_22_1","volume-title":"IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)","author":"Larson E.","year":"2001","unstructured":"E. Larson , S. Chatterjee , : A novel architecture or detailed microarchitectural modeling . In IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) , November 4-6 2001 . E. Larson, S. Chatterjee, et al. MASE: A novel architecture or detailed microarchitectural modeling. In IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), November 4-6 2001."},{"key":"e_1_3_2_1_23_1","first-page":"330","volume-title":"IEEE\/ACM International Symposium on Microarchitecture (MICRO)","author":"Lee C.","year":"1997","unstructured":"C. Lee , M. Potkonjak , : a tool for evaluating and synthesizing multimedia and communications systems . In IEEE\/ACM International Symposium on Microarchitecture (MICRO) , pages 330 -- 335 , 1997 . C. Lee, M. Potkonjak, et al. MediaBench: a tool for evaluating and synthesizing multimedia and communications systems. In IEEE\/ACM International Symposium on Microarchitecture (MICRO), pages 330--335, 1997."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.5555\/144953.144998"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339673"},{"key":"e_1_3_2_1_27_1","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"crossref","first-page":"21","DOI":"10.1007\/3-540-60294-1_95","volume-title":"International Conference on Field Programmable Logic and Applications (FPL)","author":"Payne R.","year":"1995","unstructured":"R. Payne . Self-timed FPGA systems. In W. Moore and W. Luk, editors, International Conference on Field Programmable Logic and Applications (FPL) , volume 975 of Lecture Notes in Computer Science , pages 21 -- 35 . Springer , 1995 . R. Payne. Self-timed FPGA systems. In W. Moore and W. Luk, editors, International Conference on Field Programmable Logic and Applications (FPL), volume 975 of Lecture Notes in Computer Science, pages 21--35. Springer, 1995."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/192724.192749"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.5555\/290940.290946"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859667"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2002.1012767"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.5555\/876877.879147"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/503048.503072"},{"key":"e_1_3_2_1_34_1","volume-title":"SPEC INT 95 Benchmark Suite","author":"Standard Performance Evaluation Corp.","year":"1995","unstructured":"Standard Performance Evaluation Corp. SPEC INT 95 Benchmark Suite , 1995 . Standard Performance Evaluation Corp. SPEC INT 95 Benchmark Suite, 1995."},{"key":"e_1_3_2_1_35_1","volume-title":"Performance Evaluation Corp. SPEC INT 2000 Benchmark Suite","year":"2000","unstructured":"Standard Performance Evaluation Corp. SPEC INT 2000 Benchmark Suite , 2000 . Standard Performance Evaluation Corp. SPEC INT 2000 Benchmark Suite, 2000."},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/63526.63532"},{"key":"e_1_3_2_1_37_1","first-page":"291","volume-title":"Wavescalar. In IEEE\/ACM International Symposium on Microarchitecture (MICRO)","author":"Swanson S.","year":"2003","unstructured":"S. Swanson , K. Michelson , Wavescalar. In IEEE\/ACM International Symposium on Microarchitecture (MICRO) , pages 291 -- 302 , December 2003 . S. Swanson, K. Michelson, et al. Wavescalar. In IEEE\/ACM International Symposium on Microarchitecture (MICRO), pages 291--302, December 2003."},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.5555\/998680.1006733"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2004.88"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296442"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/1084834.1084894"},{"key":"e_1_3_2_1_42_1","volume-title":"International Workshop on Logic Synthesis","author":"Venkataramani G.","year":"2004","unstructured":"G. Venkataramani , M. Budiu , to asynchronous dataflow circuits: An end-to-end toolflow . In International Workshop on Logic Synthesis , June 2004 . G. Venkataramani, M. Budiu, et al. C to asynchronous dataflow circuits: An end-to-end toolflow. In International Workshop on Logic Synthesis, June 2004."},{"key":"e_1_3_2_1_43_1","volume-title":"International Workshop on Logic Syntheis","author":"Venkataramani G.","year":"2005","unstructured":"G. Venkataramani , T. Chelcea , HLS support for unconstrained memory accesses . In International Workshop on Logic Syntheis , June 2005 . G. Venkataramani, T. Chelcea, et al. HLS support for unconstrained memory accesses. In International Workshop on Logic Syntheis, June 2005."},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1993.279484"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2003.1275745"},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339687"}],"event":{"name":"ASPLOS06: Architectural Support for Programming Languages and Operating Systems","location":"San Jose California USA","acronym":"ASPLOS06","sponsor":["SIGPLAN ACM Special Interest Group on Programming Languages","SIGOPS ACM Special Interest Group on Operating Systems","ACM Association for Computing Machinery","SIGARCH ACM Special Interest Group on Computer Architecture"]},"container-title":["Proceedings of the 12th international conference on Architectural support for programming languages and operating systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1168857.1168878","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1168857.1168878","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T11:14:09Z","timestamp":1750245249000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1168857.1168878"}},"subtitle":["evaluating spatial computation for whole program execution"],"short-title":[],"issued":{"date-parts":[[2006,10,20]]},"references-count":44,"alternative-id":["10.1145\/1168857.1168878","10.1145\/1168857"],"URL":"https:\/\/doi.org\/10.1145\/1168857.1168878","relation":{"is-identical-to":[{"id-type":"doi","id":"10.1145\/1168918.1168878","asserted-by":"object"},{"id-type":"doi","id":"10.1145\/1168917.1168878","asserted-by":"object"},{"id-type":"doi","id":"10.1145\/1168919.1168878","asserted-by":"object"}]},"subject":[],"published":{"date-parts":[[2006,10,20]]},"assertion":[{"value":"2006-10-20","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}