{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,27]],"date-time":"2026-02-27T03:46:09Z","timestamp":1772163969933,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":21,"publisher":"ACM","license":[{"start":{"date-parts":[[2006,10,20]],"date-time":"2006-10-20T00:00:00Z","timestamp":1161302400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2006,10,20]]},"DOI":"10.1145\/1168857.1168892","type":"proceedings-article","created":{"date-parts":[[2007,1,16]],"date-time":"2007-01-16T20:15:56Z","timestamp":1168978556000},"page":"274-282","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":29,"title":["Stealth prefetching"],"prefix":"10.1145","author":[{"given":"Jason F.","family":"Cantin","sequence":"first","affiliation":[{"name":"International Business Machines Corp."}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mikko H.","family":"Lipasti","sequence":"additional","affiliation":[{"name":"University of Wisconsin, Madison"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"James E.","family":"Smith","sequence":"additional","affiliation":[{"name":"University of Wisconsin, Madison"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2006,10,20]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/582034.582041"},{"key":"e_1_3_2_1_2_1","volume-title":"Technical White Paper","author":"Tendler J.","year":"2001","unstructured":"Tendler , J. , Dodson , S. , and Fields , S . IBM eServer Power4 System Microarchitecture , Technical White Paper , IBM Server Group , 2001 Tendler, J., Dodson, S., and Fields, S. IBM eServer Power4 System Microarchitecture, Technical White Paper, IBM Server Group, 2001"},{"key":"e_1_3_2_1_3_1","volume-title":"IBM Power5 Chip: A Dual-Core Multithreaded Processor IEEE Micro","author":"Kalla R.","year":"2004","unstructured":"Kalla , R. , Sinharoy , B. , and Tendler , J . IBM Power5 Chip: A Dual-Core Multithreaded Processor IEEE Micro , 2004 . Kalla, R., Sinharoy, B., and Tendler, J. IBM Power5 Chip: A Dual-Core Multithreaded Processor IEEE Micro, 2004."},{"key":"e_1_3_2_1_4_1","volume-title":"A Commodity 64 bit x86 SOC. Presentation. Advanced Micro Devices","author":"Weber F.","year":"2003","unstructured":"Weber , F. , Opteron and AMD64 , A Commodity 64 bit x86 SOC. Presentation. Advanced Micro Devices , 2003 . Weber, F., Opteron and AMD64, A Commodity 64 bit x86 SOC. Presentation. Advanced Micro Devices, 2003."},{"key":"e_1_3_2_1_5_1","volume-title":"Proceedings of the 28th International Symposium on High-Performance Computer Architecture (HPCA)","author":"Lin W-F.","year":"2001","unstructured":"Lin , W-F. , Burger , D. , Reducing DRAM Latencies with an Integrated Memory Hierarchy Design . In Proceedings of the 28th International Symposium on High-Performance Computer Architecture (HPCA) , 2001 . Lin, W-F., Burger, D., Reducing DRAM Latencies with an Integrated Memory Hierarchy Design. In Proceedings of the 28th International Symposium on High-Performance Computer Architecture (HPCA), 2001."},{"key":"e_1_3_2_1_6_1","volume-title":"Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors (ICCD)","author":"Lin W-F.","year":"2001","unstructured":"Lin , W-F. , Burger , D. , and Puzak , T ., Filtering Superfluous Prefetches using Density Vectors . In Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors (ICCD) , 2001 . Lin, W-F., Burger, D., and Puzak, T., Filtering Superfluous Prefetches using Density Vectors. In Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors (ICCD), 2001."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859663"},{"key":"e_1_3_2_1_8_1","volume-title":"Combining Software\/Hardware Prefetching and Cache Replacement. IBM Austin Center for Advanced Studies Conference (CAS)","author":"Wang Z.","year":"2004","unstructured":"Wang , Z. , McKinley , K. , and Burger , D ., Combining Software\/Hardware Prefetching and Cache Replacement. IBM Austin Center for Advanced Studies Conference (CAS) , 2004 . Wang, Z., McKinley, K., and Burger, D., Combining Software\/Hardware Prefetching and Cache Replacement. IBM Austin Center for Advanced Studies Conference (CAS), 2004."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2004.10030"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2004.11.004"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.38"},{"key":"e_1_3_2_1_12_1","volume-title":"Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)","author":"Jerger N.","year":"2006","unstructured":"Jerger , N. , Hill , E. , and Lipasti , M ., Friendly Fire: Understanding the Effects of Multiprocessor Prefetching . In Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) , 2006 . Jerger, N., Hill, E., and Lipasti, M., Friendly Fire: Understanding the Effects of Multiprocessor Prefetching. In Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2006."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.42"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.31"},{"key":"e_1_3_2_1_16_1"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/325164.325162"},{"key":"e_1_3_2_1_18_1","first-page":"13","volume-title":"Proceedings of the 5th Workshop on Computer Architecture Evaluation Using Commercial Workloads","author":"Cain H.","year":"2002","unstructured":"Cain , H. , Lepak , K. , Schwartz , B. , and Lipasti , M . Precise and Accurate Processor Simulation . In Proceedings of the 5th Workshop on Computer Architecture Evaluation Using Commercial Workloads , pp. 13 -- 22 , 2002 . Cain, H., Lepak, K., Schwartz, B., and Lipasti, M. Precise and Accurate Processor Simulation. In Proceedings of the 5th Workshop on Computer Architecture Evaluation Using Commercial Workloads, pp. 13--22, 2002."},{"key":"e_1_3_2_1_19_1","unstructured":"Keller T. Maynard A. Simpson R. and Bohrer P. Simosppc Full System Simulator. http:\/\/www.cs.utexas.edu\/users\/cart\/simOS.  Keller T. Maynard A. Simpson R. and Bohrer P. Simosppc Full System Simulator. http:\/\/www.cs.utexas.edu\/users\/cart\/simOS."},{"key":"e_1_3_2_1_20_1","volume-title":"User's Manual Supplement","author":"Ultra SPARC IV","year":"2004","unstructured":"Ultra SPARC IV Processor , User's Manual Supplement , Sun Microsystems Inc , 2004 . UltraSPARC IV Processor, User's Manual Supplement, Sun Microsystems Inc, 2004."},{"key":"e_1_3_2_1_21_1","volume-title":"Proceedings of the International Conference on Parallel Processing (ICPP)","author":"Gharachorloo K.","year":"1991","unstructured":"Gharachorloo , K. , Gupta , A. , and Hennessy , J . Two Techniques to Enhance the Performance of Memory Consistency Models . In Proceedings of the International Conference on Parallel Processing (ICPP) , 1991 . Gharachorloo, K., Gupta, A., and Hennessy, J. Two Techniques to Enhance the Performance of Memory Consistency Models. In Proceedings of the International Conference on Parallel Processing (ICPP), 1991."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2003.1178046"}],"event":{"name":"ASPLOS06: Architectural Support for Programming Languages and Operating Systems","location":"San Jose California USA","acronym":"ASPLOS06","sponsor":["SIGPLAN ACM Special Interest Group on Programming Languages","SIGOPS ACM Special Interest Group on Operating Systems","ACM Association for Computing Machinery","SIGARCH ACM Special Interest Group on Computer Architecture"]},"container-title":["Proceedings of the 12th international conference on Architectural support for programming languages and operating systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1168857.1168892","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1168857.1168892","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T11:14:09Z","timestamp":1750245249000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1168857.1168892"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006,10,20]]},"references-count":21,"alternative-id":["10.1145\/1168857.1168892","10.1145\/1168857"],"URL":"https:\/\/doi.org\/10.1145\/1168857.1168892","relation":{"is-identical-to":[{"id-type":"doi","id":"10.1145\/1168918.1168892","asserted-by":"object"},{"id-type":"doi","id":"10.1145\/1168917.1168892","asserted-by":"object"},{"id-type":"doi","id":"10.1145\/1168919.1168892","asserted-by":"object"}]},"subject":[],"published":{"date-parts":[[2006,10,20]]},"assertion":[{"value":"2006-10-20","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}