{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T18:49:09Z","timestamp":1730314149425,"version":"3.28.0"},"publisher-location":"New York, NY, USA","reference-count":33,"publisher":"ACM","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2006,10,22]]},"DOI":"10.1145\/1176760.1176764","type":"proceedings-article","created":{"date-parts":[[2007,1,17]],"date-time":"2007-01-17T01:15:56Z","timestamp":1168996556000},"page":"13-23","update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Reaching fast code faster"],"prefix":"10.1145","author":[{"given":"Won","family":"So","sequence":"first","affiliation":[{"name":"North Carolina State University, Raleigh, NC"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alexander G.","family":"Dean","sequence":"additional","affiliation":[{"name":"North Carolina State University, Raleigh, NC"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2006,10,22]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Loop quantization: an analysis and algorithm. Technical report","author":"Aiken A.","year":"1987","unstructured":"A. Aiken and A. Nicolau . Loop quantization: an analysis and algorithm. Technical report , Cornell University , Ithaca, NY, USA , 1987 . A. Aiken and A. Nicolau. Loop quantization: an analysis and algorithm. Technical report, Cornell University, Ithaca, NY, USA, 1987."},{"key":"e_1_3_2_1_2_1","first-page":"1","volume-title":"Design and Optimization of Compilers","author":"Allen F.","year":"1972","unstructured":"F. Allen and J. Cocke . A catalogue of optimizing transformations . In Design and Optimization of Compilers , pages 1 -- 30 . Prentice-Hall , 1972 . F. Allen and J. Cocke. A catalogue of optimizing transformations. In Design and Optimization of Compilers, pages 1--30. Prentice-Hall, 1972."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/567067.567085"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/53990.54014"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.5555\/144953.145001"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/93542.93553"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1016\/0743-7315(88)90002-0"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/795698.798430"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.5555\/266800.266835"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2005.16"},{"key":"e_1_3_2_1_11_1","volume-title":"Three superblock scheduling models for superscalar and superpipelined processors. Technical report","author":"Chang P. P.","year":"1991","unstructured":"P. P. Chang , N. J. Warter , S. Mahlke , W. Y. Chen , and W. W. Hwu . Three superblock scheduling models for superscalar and superpipelined processors. Technical report , University of Illinois , Urbana, IL , Dec. 1991 . P. P. Chang, N. J. Warter, S. Mahlke, W. Y. Chen, and W. W. Hwu. Three superblock scheduling models for superscalar and superpipelined processors. Technical report, University of Illinois, Urbana, IL, Dec. 1991."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/C-M.1981.220595"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/32.121752"},{"issue":"7","key":"e_1_3_2_1_14_1","first-page":"278","article-title":"A technique for global microcode compaction","volume":"30","author":"Fisher J. A.","year":"1981","unstructured":"J. A. Fisher . Trace scheduling : A technique for global microcode compaction . IEEE Transactions on Computers , 30 ( 7 ): 278 -- 490 , 1981 . J. A. Fisher. Trace scheduling: A technique for global microcode compaction. IEEE Transactions on Computers, 30(7):278--490, 1981.","journal-title":"IEEE Transactions on Computers"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/32.54294"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.5555\/1128020.1128563"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.5555\/225160.225189"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.5555\/822079.822721"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/73141.74840"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF01205185"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/53990.54022"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/144965.144998"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/513829.513850"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.5555\/645989.674315"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.5555\/800075.802449"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.5555\/800048.801721"},{"key":"e_1_3_2_1_27_1","first-page":"27","volume-title":"Proceedings of Seventh Workshop on Interaction between Compilers and Computer Architecture (INTERACT-7)","author":"So W.","year":"2003","unstructured":"W. So and A. G. Dean . Procedure cloning and integration for converting parallelism from coarse to fine grain . In Proceedings of Seventh Workshop on Interaction between Compilers and Computer Architecture (INTERACT-7) , pages 27 -- 36 . IEEE Computer Society , Feb. 2003 . W. So and A. G. Dean. Procedure cloning and integration for converting parallelism from coarse to fine grain. In Proceedings of Seventh Workshop on Interaction between Compilers and Computer Architecture (INTERACT-7), pages 27--36. IEEE Computer Society, Feb. 2003."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065910.1065930"},{"key":"e_1_3_2_1_29_1","volume-title":"Apr.","author":"Instruments Texas","year":"2002","unstructured":"Texas Instruments . TMS320C64x DSP Library Programmer's Reference , Apr. 2002 . Texas Instruments. TMS320C64x DSP Library Programmer's Reference, Apr. 2002."},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.5555\/144953.145796"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/155090.155118"},{"key":"e_1_3_2_1_32_1","first-page":"90","volume-title":"Proceedings of the 2001 IASTED International Conference on Parallel and Distributed Computing and systems (PDCS '01)","author":"Way T.","year":"2001","unstructured":"T. Way , B. Breech , and L. Pollock . Demand-driven inlining heuristics in a region-based optimizing compiler for ILP architectures . In Proceedings of the 2001 IASTED International Conference on Parallel and Distributed Computing and systems (PDCS '01) , pages 90 -- 95 , Anaheim, CA, USA , Aug. 2001 . T. Way, B. Breech, and L. Pollock. Demand-driven inlining heuristics in a region-based optimizing compiler for ILP architectures. In Proceedings of the 2001 IASTED International Conference on Parallel and Distributed Computing and systems (PDCS '01), pages 90--95, Anaheim, CA, USA, Aug. 2001."},{"key":"e_1_3_2_1_33_1","first-page":"40","volume-title":"Workshop on Profile and Feedback-Directed Compilation","author":"Way T.","year":"1998","unstructured":"T. Way and L. Pollock . Using path spectra to direct function cloning . In Workshop on Profile and Feedback-Directed Compilation , pages 40 -- 47 , Oct. 1998 . T. Way and L. Pollock. Using path spectra to direct function cloning. In Workshop on Profile and Feedback-Directed Compilation, pages 40--47, Oct. 1998."}],"event":{"name":"ESWEEK06: Second Embedded Systems Week 2006","sponsor":["ACM Association for Computing Machinery","SIGBED ACM Special Interest Group on Embedded Systems","SIGDA ACM Special Interest Group on Design Automation","SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"],"location":"Seoul Korea","acronym":"ESWEEK06"},"container-title":["Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1176760.1176764","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,7]],"date-time":"2023-01-07T21:01:20Z","timestamp":1673125280000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1176760.1176764"}},"subtitle":["using modeling for efficient software thread integration on a VLIW DSP"],"short-title":[],"issued":{"date-parts":[[2006,10,22]]},"references-count":33,"alternative-id":["10.1145\/1176760.1176764","10.1145\/1176760"],"URL":"https:\/\/doi.org\/10.1145\/1176760.1176764","relation":{},"subject":[],"published":{"date-parts":[[2006,10,22]]},"assertion":[{"value":"2006-10-22","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}