{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T18:49:10Z","timestamp":1730314150930,"version":"3.28.0"},"publisher-location":"New York, NY, USA","reference-count":23,"publisher":"ACM","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2006,10,22]]},"DOI":"10.1145\/1176760.1176768","type":"proceedings-article","created":{"date-parts":[[2007,1,16]],"date-time":"2007-01-16T20:15:56Z","timestamp":1168978556000},"page":"43-53","update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["Adapting compilation techniques to enhance the packing of instructions into registers"],"prefix":"10.1145","author":[{"given":"Stephen","family":"Hines","sequence":"first","affiliation":[{"name":"Florida State University, Tallahassee, FL"}]},{"given":"David","family":"Whalley","sequence":"additional","affiliation":[{"name":"Florida State University, Tallahassee, FL"}]},{"given":"Gary","family":"Tyson","sequence":"additional","affiliation":[{"name":"Florida State University, Tallahassee, FL"}]}],"member":"320","published-online":{"date-parts":[[2006,10,22]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.982917"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/53990.54023"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339657"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/301618.301655"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/780732.780765"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/349214.349233"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/502874.502886"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/950162.950163"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.5555\/1128020.1128563"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.32"},{"key":"e_1_3_2_1_11_1","first-page":"160","volume-title":"Proceedings of the 2nd Watson Conference on Interaction between Architecture, Circuits, and Compilers","author":"Hines S.","year":"2005","unstructured":"S. Hines , G. Tyson , and D. Whalley . Improving the energy and execution efficiency of a small instruction cache by using an instruction register file . In Proceedings of the 2nd Watson Conference on Interaction between Architecture, Circuits, and Compilers , pages 160 -- 169 , September 2005 . S. Hines, G. Tyson, and D. Whalley. Improving the energy and execution efficiency of a small instruction cache by using an instruction register file. In Proceedings of the 2nd Watson Conference on Interaction between Architecture, Circuits, and Compilers, pages 160--169, September 2005."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2005.27"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/266800.266818"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/313817.313944"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.5555\/266800.266819"},{"issue":"1","key":"e_1_3_2_1_16_1","first-page":"49","article-title":"A 160-mhz, 32-b, 0. 5-W CMOS RISC microprocessor","volume":"9","year":"1997","unstructured":"Montanaro J., A 160-mhz, 32-b, 0. 5-W CMOS RISC microprocessor . Digital Tech. J. , 9 ( 1 ): 49 -- 62 , 1997 . Montanaro J., et al. A 160-mhz, 32-b, 0. 5-W CMOS RISC microprocessor. Digital Tech. J., 9(1):49--62, 1997.","journal-title":"Digital Tech. J."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/7902.7904"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/502217.502244"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/93542.93550"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.464580"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.5555\/144953.145796"},{"key":"e_1_3_2_1_22_1","volume-title":"The SPARC Architecture Manual","author":"Weaver D.","year":"1994","unstructured":"D. Weaver and T. Germond . The SPARC Architecture Manual , 1994 . D. Weaver and T. Germond. The SPARC Architecture Manual, 1994."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.509850"}],"event":{"name":"ESWEEK06: Second Embedded Systems Week 2006","sponsor":["ACM Association for Computing Machinery","SIGBED ACM Special Interest Group on Embedded Systems","SIGDA ACM Special Interest Group on Design Automation","SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"],"location":"Seoul Korea","acronym":"ESWEEK06"},"container-title":["Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1176760.1176768","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,7]],"date-time":"2023-01-07T16:01:32Z","timestamp":1673107292000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1176760.1176768"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006,10,22]]},"references-count":23,"alternative-id":["10.1145\/1176760.1176768","10.1145\/1176760"],"URL":"https:\/\/doi.org\/10.1145\/1176760.1176768","relation":{},"subject":[],"published":{"date-parts":[[2006,10,22]]},"assertion":[{"value":"2006-10-22","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}