{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:53:03Z","timestamp":1750308783670,"version":"3.41.0"},"reference-count":12,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2006,10,1]],"date-time":"2006-10-01T00:00:00Z","timestamp":1159660800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2006,10]]},"abstract":"<jats:p>Logic duplication, a commonly used synthesis technique to remove trapped inverters in reconvergent paths of Domino circuits, incurs high area and power penalties. In this article, we propose a synthesis scheme to reduce the duplication cost by allowing inverters in Domino logic under certain timing constraints for both simple and complex gates. Moreover, we can include the logic duplication minimization during technology mapping for synthesis of Domino circuits with complex gates. In order to guarantee the robustness of such Domino circuits, we perform the logic optimization as a postlayout step. Experimental results show significant reduction in duplication cost, which translates into significant improvements in area and power. As a byproduct, the timing performance is also improved owing to smaller layout area and\/or logic depth.<\/jats:p>","DOI":"10.1145\/1179461.1179462","type":"journal-article","created":{"date-parts":[[2007,1,16]],"date-time":"2007-01-16T19:38:29Z","timestamp":1168976309000},"page":"797-821","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Postlayout optimization for synthesis of Domino circuits"],"prefix":"10.1145","volume":"11","author":[{"given":"Aiqun","family":"Cao","sequence":"first","affiliation":[{"name":"Synopsys, Inc., Mountain View, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ruibing","family":"Lu","sequence":"additional","affiliation":[{"name":"Synopsys, Inc., Mountain View, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chen","family":"Li","sequence":"additional","affiliation":[{"name":"Purdue University, West Lafayette, IN"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Cheng-Kok","family":"Koh","sequence":"additional","affiliation":[{"name":"Purdue University, West Lafayette, IN"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2006,10]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Proceedings of the IEEE\/ACM International Conference on Computer Aided Design. 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In Proceedings of the ACM\/IEEE Conference on Design Automation. ACM Press , New York, 820--825. 10.1145\/996566.996786 Cao, A. and Koh, C.-K. 2004. Post-layout logic optimization of Domino circuits. In Proceedings of the ACM\/IEEE Conference on Design Automation. ACM Press, New York, 820--825. 10.1145\/996566.996786"},{"key":"e_1_2_1_3_1","volume-title":"Proceedings of the Asia South Pacific Design Automation Conference. IEEE Computer Society Press","author":"Cao A.","year":"2072","unstructured":"Cao , A. , Lu , R. , and Koh , C . -K. 2005. Post-layout logic duplication for synthesis of Domino circuits with complex gates . In Proceedings of the Asia South Pacific Design Automation Conference. IEEE Computer Society Press , Los Alamitos, CA, 260--265. 10.1145\/11 2072 5.1120845 Cao, A., Lu, R., and Koh, C.-K. 2005. Post-layout logic duplication for synthesis of Domino circuits with complex gates. In Proceedings of the Asia South Pacific Design Automation Conference. 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