{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:40:49Z","timestamp":1750308049660,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":47,"publisher":"ACM","license":[{"start":{"date-parts":[[2006,6,28]],"date-time":"2006-06-28T00:00:00Z","timestamp":1151452800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2006,6,28]]},"DOI":"10.1145\/1183401.1183436","type":"proceedings-article","created":{"date-parts":[[2007,1,17]],"date-time":"2007-01-17T01:15:56Z","timestamp":1168996556000},"page":"239-248","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":19,"title":["Heterogeneous way-size cache"],"prefix":"10.1145","author":[{"given":"Jaume","family":"Abella","sequence":"first","affiliation":[{"name":"Intel Labs - UPC, Barcelona (Spain)"}]},{"given":"Antonio","family":"Gonz\u00e1lez","sequence":"additional","affiliation":[{"name":"Universitat Polit\u00e8cnica de Catalunya, Barcelona (Spain)"}]}],"member":"320","published-online":{"date-parts":[[2006,6,28]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Power Efficient Data Cache Designs. In ICCD","author":"Abella J.","year":"2003","unstructured":"J. Abella , A. Gonz\u00e1lez . Power Efficient Data Cache Designs. In ICCD 2003 . J. Abella, A. Gonz\u00e1lez. Power Efficient Data Cache Designs. In ICCD 2003."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1061267.1061271"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/513918.514037"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/165123.165153"},{"key":"e_1_3_2_1_5_1","volume-title":"Selective Cache Ways: On-Demand Cache Resource Allocation. In MICRO","author":"Albonesi D. H.","year":"1999","unstructured":"D. H. Albonesi . Selective Cache Ways: On-Demand Cache Resource Allocation. In MICRO 1999 . D. H. Albonesi. Selective Cache Ways: On-Demand Cache Resource Allocation. In MICRO 1999."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/360128.360153"},{"key":"e_1_3_2_1_7_1","volume-title":"Vijaykumar. Reactive-Associative Caches. In PACT","author":"Batson B.","year":"2001","unstructured":"B. Batson , T. N. Vijaykumar. Reactive-Associative Caches. In PACT 2001 . B. Batson, T. N. Vijaykumar. Reactive-Associative Caches. In PACT 2001."},{"key":"e_1_3_2_1_8_1","volume-title":"Wood. TLC: Transmission Line Caches. In MICRO","author":"Beckmann B. M.","year":"2003","unstructured":"B. M. Beckmann , D. A. Wood. TLC: Transmission Line Caches. In MICRO 2003 . B. M. Beckmann, D. A. Wood. TLC: Transmission Line Caches. In MICRO 2003."},{"key":"e_1_3_2_1_9_1","volume-title":"Version 3.0. Technical report, Computer Sciences Department","author":"Burger D.","year":"1999","unstructured":"D. Burger and T. Austin . The SimpleScalar Tool Set , Version 3.0. Technical report, Computer Sciences Department , University of Wisconsin-Madison , 1999 . D. Burger and T. Austin. The SimpleScalar Tool Set, Version 3.0. Technical report, Computer Sciences Department, University of Wisconsin-Madison, 1999."},{"key":"e_1_3_2_1_10_1","author":"Calder B.","year":"1996","unstructured":"B. Calder , D. Grunwald , J. Emer. Predictive Sequential Associative Cache. In HPCA 1996 . B. Calder, D. Grunwald, J. Emer. Predictive Sequential Associative Cache. In HPCA 1996.","journal-title":"J. Emer. Predictive Sequential Associative Cache. In HPCA"},{"key":"e_1_3_2_1_11_1","volume-title":"Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures. In MICRO","author":"Chishti Z.","year":"2003","unstructured":"Z. Chishti , M. D. Powell , T. N. Vijaykumar . Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures. In MICRO 2003 . Z. Chishti, M. D. Powell, T. N. Vijaykumar. Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures. In MICRO 2003."},{"key":"e_1_3_2_1_12_1","volume-title":"ISCA","author":"Dhodapkar A. S.","year":"2002","unstructured":"A. S. Dhodapkar , J. E. Smith . Managing Multi-Configuration Hardware via Dynamic Working Set Analysis . In ISCA 2002 . A. S. Dhodapkar, J. E. Smith. Managing Multi-Configuration Hardware via Dynamic Working Set Analysis. In ISCA 2002."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/645989.674326"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.5555\/545215.545232"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/313817.313860"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/224538.224622"},{"key":"e_1_3_2_1_17_1","volume-title":"Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines. In ISCA","author":"Heo S.","year":"2003","unstructured":"S. Heo , K. Barr , M. Hampton , K. Asanovic . Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines. In ISCA 2003 . S. Heo, K. Barr, M. Hampton, K. Asanovic. Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines. In ISCA 2003."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/330855.331018"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/383082.383086"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/313817.313948"},{"key":"e_1_3_2_1_21_1","volume-title":"Cost-Sensitive Cache Replacement Algorithms. In HPCA","author":"Jeong J.","year":"2003","unstructured":"J. Jeong , M. Dubois . Cost-Sensitive Cache Replacement Algorithms. In HPCA 2003 . J. Jeong, M. Dubois. Cost-Sensitive Cache Replacement Algorithms. In HPCA 2003."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/232973.232986"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379268"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/74925.74941"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2004.10015"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605420"},{"key":"e_1_3_2_1_27_1","volume-title":"Drowsy Instruction Caches. Leakage Power Reduction Using Dynamic Voltage Scaling and Cache Sub-bank Prediction. In MICRO","author":"Kim N. S.","year":"2002","unstructured":"N. S. Kim , K. Flautner , D. Blaauw , T. Mudge . Drowsy Instruction Caches. Leakage Power Reduction Using Dynamic Voltage Scaling and Cache Sub-bank Prediction. In MICRO 2002 . N. S. Kim, K. Flautner, D. Blaauw, T. Mudge. Drowsy Instruction Caches. Leakage Power Reduction Using Dynamic Voltage Scaling and Cache Sub-bank Prediction. In MICRO 2002."},{"key":"e_1_3_2_1_28_1","volume-title":"W. H. Mangione-Smith. The Filter Cache: An Energy Efficient Memory Structure. In MICRO","author":"Kin J.","year":"1997","unstructured":"J. Kin , M. Gupta , W. H. Mangione-Smith. The Filter Cache: An Energy Efficient Memory Structure. In MICRO 1997 . J. Kin, M. Gupta, W. H. Mangione-Smith. The Filter Cache: An Energy Efficient Memory Structure. In MICRO 1997."},{"key":"e_1_3_2_1_29_1","volume-title":"Leakage Energy Management in Cache Hierarchies. In PACT","author":"Li L.","year":"2002","unstructured":"L. Li , I. Kadayif , Y-F. Tsai , N. Vijaykrishnan , M. Kandemir , M. J. Irwin , A. Sivasubramaniam . Leakage Energy Management in Cache Hierarchies. In PACT 2002 . L. Li, I. Kadayif, Y-F. Tsai, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, A. Sivasubramaniam. Leakage Energy Management in Cache Hierarchies. In PACT 2002."},{"key":"e_1_3_2_1_30_1","volume-title":"W. H. Mangione-Smith. Just Say No: Benefits of Early Cache Miss Determination. In HPCA","author":"Memik G.","year":"2003","unstructured":"G. Memik , G. Reinman , W. H. Mangione-Smith. Just Say No: Benefits of Early Cache Miss Determination. In HPCA 2003 . G. Memik, G. Reinman, W. H. Mangione-Smith. Just Say No: Benefits of Early Cache Miss Determination. In HPCA 2003."},{"key":"e_1_3_2_1_31_1","volume-title":"ISLPED","author":"Powell M.","year":"2000","unstructured":"M. Powell , A. Agarwal , T. N. Vijaykumar , B. Falsafi , K. Roy . Reducing Set-Associative Cache Energy via Way-Prediction and Selective Direct-Mapping . In ISLPED 2000 . M. Powell, A. Agarwal, T. N. Vijaykumar, B. Falsafi, K. Roy. Reducing Set-Associative Cache Energy via Way-Prediction and Selective Direct-Mapping. In ISLPED 2000."},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/344166.344526"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/305138.305158"},{"key":"e_1_3_2_1_34_1","volume-title":"DASC Cache. In HPCA","author":"Seznec A.","year":"1995","unstructured":"A. Seznec . DASC Cache. In HPCA 1995 . A. Seznec. DASC Cache. In HPCA 1995."},{"key":"e_1_3_2_1_35_1","volume-title":"An Integrated Cache Timing, Power and Area Model. Research report 2001\/2","author":"Shivakumar P.","year":"2001","unstructured":"P. Shivakumar , N. P. Jouppi . CACTI 3.0 : An Integrated Cache Timing, Power and Area Model. Research report 2001\/2 , WRL, Palo Alto, CA (USA) , 2001 . P. Shivakumar, N. P. Jouppi. CACTI 3.0: An Integrated Cache Timing, Power and Area Model. Research report 2001\/2, WRL, Palo Alto, CA (USA), 2001."},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/224081.224093"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.5555\/266800.266808"},{"key":"e_1_3_2_1_38_1","volume-title":"The Minimax Cache: An Energy-Efficient Framework for Media Processors. In HPCA","author":"Unsal O. S.","year":"2002","unstructured":"O. S. Unsal , I. Koren , C. M. Krishna , C. A. Moritz . The Minimax Cache: An Energy-Efficient Framework for Media Processors. In HPCA 2002 . O. S. Unsal, I. Koren, C. M. Krishna, C. A. Moritz. The Minimax Cache: An Energy-Efficient Framework for Media Processors. In HPCA 2002."},{"key":"e_1_3_2_1_39_1","volume-title":"PACT","author":"Wang Z.","year":"2002","unstructured":"Z. Wang , K. S. McKinley , A. L. Rosenberg , C. C. Weems . Using the Compiler to Improve Cache Replacement Decisions . In PACT 2002 . Z. Wang, K. S. McKinley, A. L. Rosenberg, C. C. Weems. Using the Compiler to Improve Cache Replacement Decisions. In PACT 2002."},{"key":"e_1_3_2_1_40_1","volume-title":"Direct Addressed Caches for Reduced Power Consumption. In MICRO","author":"Witchel E.","year":"2001","unstructured":"E. Witchel , S. Larsen , C. S. Ananian , K. Asanovic . Direct Addressed Caches for Reduced Power Consumption. In MICRO 2001 . E. Witchel, S. Larsen, C. S. Ananian, K. Asanovic. Direct Addressed Caches for Reduced Power Consumption. In MICRO 2001."},{"key":"e_1_3_2_1_41_1","volume-title":"J-L. Baer. Modified LRU Policies for Improving Second-level Cache Behavior. In HPCA","author":"Wong W. A.","year":"2000","unstructured":"W. A. Wong , J-L. Baer. Modified LRU Policies for Improving Second-level Cache Behavior. In HPCA 2000 . W. A. Wong, J-L. Baer. Modified LRU Policies for Improving Second-level Cache Behavior. In HPCA 2000."},{"key":"e_1_3_2_1_42_1","volume-title":"HPCA","author":"Yang S. H.","year":"2002","unstructured":"S. H. Yang , M. D. Powell , B. Falsafi , T. N. Vijaykumar . Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay . In HPCA 2002 . S. H. Yang, M. D. Powell, B. Falsafi, T. N. Vijaykumar. Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay. In HPCA 2002."},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859635"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.621212"},{"key":"e_1_3_2_1_45_1","volume-title":"Compiler-Directed Instruction Cache Leakage Optimization. In MICRO","author":"Zhang W.","year":"2002","unstructured":"W. Zhang , J. S. Hu , V. Degalahal , M. Kandemir , N. Vijaykrishnan , M. J. Irwin . Compiler-Directed Instruction Cache Leakage Optimization. In MICRO 2002 . W. Zhang, J. S. Hu, V. Degalahal, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. Compiler-Directed Instruction Cache Leakage Optimization. In MICRO 2002."},{"key":"e_1_3_2_1_46_1","volume-title":"Adaptive Mode Control: A Static-Power-Efficient Cache Design. In PACT","author":"Zhou H.","year":"2001","unstructured":"H. Zhou , M. Toburen , E. Rotenberg , T. Conte . Adaptive Mode Control: A Static-Power-Efficient Cache Design. In PACT 2001 . H. Zhou, M. Toburen, E. Rotenberg, T. Conte. Adaptive Mode Control: A Static-Power-Efficient Cache Design. In PACT 2001."},{"key":"e_1_3_2_1_47_1","unstructured":"SPEC 2000. http:\/\/www.specbench.org\/osg\/cpu2000\/  SPEC 2000. http:\/\/www.specbench.org\/osg\/cpu2000\/"}],"event":{"name":"ICS06: International Conference on Supercomputing 2006","sponsor":["ACM Association for Computing Machinery","SIGARCH ACM Special Interest Group on Computer Architecture"],"location":"Cairns Queensland Australia","acronym":"ICS06"},"container-title":["Proceedings of the 20th annual international conference on Supercomputing"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1183401.1183436","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1183401.1183436","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T15:14:36Z","timestamp":1750259676000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1183401.1183436"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006,6,28]]},"references-count":47,"alternative-id":["10.1145\/1183401.1183436","10.1145\/1183401"],"URL":"https:\/\/doi.org\/10.1145\/1183401.1183436","relation":{},"subject":[],"published":{"date-parts":[[2006,6,28]]},"assertion":[{"value":"2006-06-28","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}