{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,1,3]],"date-time":"2023-01-03T11:17:14Z","timestamp":1672744634164},"reference-count":24,"publisher":"Association for Computing Machinery (ACM)","issue":"4","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGARCH Comput. Archit. News"],"published-print":{"date-parts":[[1998,9]]},"abstract":"<jats:p>Speculative instructions execution requires dynamic branch predictors to increase the performance of a processor by executing from predicted branch target routines. Conventional Scalar architectures such as the Superscalar or Multiscalar architecture executes from a single stream, while a Multithreaded architecture executes from multiple streams at a time. Several aggressive branch predictors have been proposed with high prediction accuracies. Unfortunately, none of the branch predictors can provide 100% accuracy. Therefore, there is an inherent limitation on speculative execution in real implementation. In this paper, we show that Multithreaded architecture is a better candidate for utilizing speculative execution than Scalar architectures. Generally the branch prediction performance degradation is compounded for larger window sizes on Scalar architectures, while for a Multithreaded architecture, by increasing the number of executing threads, we could sustain a higher performance for a large aggregated speculative window size. Hence, heavier workloads may increase performance and utilization for Multithreaded architectures. We present analytical and simulation results to support our argument.<\/jats:p>","DOI":"10.1145\/1216475.1216476","type":"journal-article","created":{"date-parts":[[2007,4,5]],"date-time":"2007-04-05T19:52:18Z","timestamp":1175802738000},"page":"3-11","update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["A comparison of the effect of branch prediction on multithreaded and scalar architectures"],"prefix":"10.1145","volume":"26","author":[{"given":"Prasad N.","family":"Golla","sequence":"first","affiliation":[{"name":"Southern Methodist University, Dallas TX"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Eric C.","family":"Lin","sequence":"additional","affiliation":[{"name":"Southern Methodist University, Dallas TX"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[1998,9]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/165123.165161"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/143365.143490"},{"key":"e_1_2_1_3_1","first-page":"07632","author":"Johnson Mike","year":"1991","unstructured":"Mike Johnson , \" Superscalar Microprocessor Design ,\" P T R Prentice-Hall , Inc. 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Peter Song \"Multithreading Comes of Age \" MicroProcessor Report pp. 13--18 July 14th 1997."},{"issue":"2","key":"e_1_2_1_10_1","first-page":"108","volume":"19","author":"Bershad T. E.","year":"1991","unstructured":"T. E. Anderson H. L. Levy B. N. Bershad and E. D. Lazowska , \"The Interaction of Architecture and Operating System Design,\" Computer Architecture News , Vol. 19 , No. 2 , pp. 108 -- 120 , 1991 . T. E. Anderson H. L. Levy B. N. Bershad and E. D. Lazowska, \"The Interaction of Architecture and Operating System Design,\" Computer Architecture News, Vol. 19, No. 2, pp. 108--120, 1991.","journal-title":"\"The Interaction of Architecture and Operating System Design,\" Computer Architecture News"},{"key":"e_1_2_1_11_1","unstructured":"Tera Computer Company \"Press Releases \" http:\/\/www.tera.com\/ 1997.  Tera Computer Company \"Press Releases \" http:\/\/www.tera.com\/ 1997."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/232973.232994"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/225830.224449"},{"key":"e_1_2_1_14_1","first-page":"6","volume-title":"Proceedings of the 1978 International Conference on Parallel Processing","author":"Smith B. J.","year":"1978","unstructured":"B. J. Smith , \" A Pipelined , Shared Resource MIMD Computer ,\" Proceedings of the 1978 International Conference on Parallel Processing , pages 6 -- 9 , 1978 . B. J. Smith, \"A Pipelined, Shared Resource MIMD Computer,\" Proceedings of the 1978 International Conference on Parallel Processing, pages 6--9, 1978."},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/223982.223985"},{"key":"e_1_2_1_16_1","volume-title":"May, 1996.","author":"Jack","unstructured":"Jack L. Lo et al., \"Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading,\" International Symposium on Computer Architecture , May, 1996. Jack L. Lo et al., \"Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading,\" International Symposium on Computer Architecture, May, 1996."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/77726.255132"},{"key":"e_1_2_1_18_1","volume-title":"Superscalar Processors,\" 27th Hawaii International Conference on System Sciences","author":"Wayne Yamamoto","year":"1994","unstructured":"Wayne Yamamoto et al , \" Performance Estimation of Multistreamed , Superscalar Processors,\" 27th Hawaii International Conference on System Sciences , pages I:195--204, Jan. , 1994 . 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