{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T13:57:25Z","timestamp":1742392645179},"reference-count":35,"publisher":"Association for Computing Machinery (ACM)","issue":"1","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2007,3]]},"abstract":"<jats:p>Network processors (NPs) have emerged as successful platforms for providing both high performance and flexibility in building powerful routers. Typical NPs incorporate multiprocessing and multithreading to achieve maximum parallel processing capabilities. We observed that under low incoming traffic rates, processing elements (PEs) in an NP are idle for most of the time but still consume dynamic power. This paper develops a low-power technique to reduce the activities of PEs in accordance with the varying traffic volume. We propose to monitor the average number of idle threads in a time window, and gate off the clock signals to unnecessary PEs when a subset of PEs is enough to handle the network traffic. We solve the difficulties arising from clock gating the PEs, such as redirecting network packets, determining the thresholds of turning on\/off PEs, and avoiding unnecessary packet loss. Our technique brings significant reduction in power consumption of NPs with no packet loss and little impact on overall throughput.<\/jats:p>","DOI":"10.1145\/1216544.1216547","type":"journal-article","created":{"date-parts":[[2007,4,5]],"date-time":"2007-04-05T19:20:08Z","timestamp":1175800808000},"page":"4","update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":24,"title":["Conserving network processor power consumption by exploiting traffic variability"],"prefix":"10.1145","volume":"4","author":[{"given":"Yan","family":"Luo","sequence":"first","affiliation":[{"name":"University of Massachusetts Lowell, Lowell, MA"}]},{"given":"Jia","family":"Yu","sequence":"additional","affiliation":[{"name":"University of California Riverside, Reverside California"}]},{"given":"Jun","family":"Yang","sequence":"additional","affiliation":[{"name":"University of Pittsburgh, Pittsburgh, Pennsylvania"}]},{"given":"Laxmi N.","family":"Bhuyan","sequence":"additional","affiliation":[{"name":"University of California Riverside, Reverside California"}]}],"member":"320","published-online":{"date-parts":[[2007,3]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Amcc np7510 product manual","unstructured":"AMCC. 2002. Amcc np7510 product manual . Applied Micro Circuits Corp. Sunnyvale, CA. AMCC. 2002. Amcc np7510 product manual. Applied Micro Circuits Corp. Sunnyvale, CA."},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.36"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339657"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/977091.977125"},{"key":"e_1_2_1_5_1","unstructured":"Cisco. Cisco crs-1 carrier routing system 8-slot line card chassis system description.  Cisco. Cisco crs-1 carrier routing system 8-slot line card chassis system description."},{"key":"e_1_2_1_6_1","volume-title":"Proceedings of International Conference on VLSI Design.","author":"Duarte D.","unstructured":"Duarte , D. , Tsai , Y. , Vijaykrishnan , N. , and Irwin , M . 2002a. Evaluating run-time techniques for leakage power reduction . In Proceedings of International Conference on VLSI Design. Duarte, D., Tsai, Y., Vijaykrishnan, N., and Irwin, M. 2002a. Evaluating run-time techniques for leakage power reduction. In Proceedings of International Conference on VLSI Design."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2002.808433"},{"key":"e_1_2_1_8_1","volume-title":"Workshop on Network Processors in conjunction with Ninth International Symposium on High Performance Computer Architecture (HPCA-9). 10--22","author":"Franklin M.","unstructured":"Franklin , M. and Wolf , T . 2003. Power considerations in network processor design . In Workshop on Network Processors in conjunction with Ninth International Symposium on High Performance Computer Architecture (HPCA-9). 10--22 . Franklin, M. and Wolf, T. 2003. Power considerations in network processor design. In Workshop on Network Processors in conjunction with Ninth International Symposium on High Performance Computer Architecture (HPCA-9). 10--22."},{"key":"e_1_2_1_9_1","first-page":"12","article-title":"Intel network processor targets routers","volume":"13","author":"Halfhill T.","year":"1999","unstructured":"Halfhill , T. 1999 . Intel network processor targets routers . Microprocessor Report 13 , 12 (Sept). Halfhill, T. 1999. Intel network processor targets routers. Microprocessor Report 13, 12 (Sept).","journal-title":"Microprocessor Report"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859653"},{"key":"e_1_2_1_11_1","volume-title":"Hifn 5np4g network processor data sheet","author":"Hifn","unstructured":"Hifn . Hifn 5np4g network processor data sheet . Hifn Corporation , Los Gatos, CA . Hifn. Hifn 5np4g network processor data sheet. Hifn Corporation, Los Gatos, CA."},{"key":"e_1_2_1_12_1","volume-title":"Ixp1200 network processor family hardware reference manual","author":"Intel 0.","unstructured":"Intel . 200 0. Ixp1200 network processor family hardware reference manual . Intel Corporation , Santa Clara , California. Intel. 2000. Ixp1200 network processor family hardware reference manual. Intel Corporation, Santa Clara, California."},{"key":"e_1_2_1_13_1","volume-title":"Intel ixp2xxx product line of network processors","author":"Intel","unstructured":"Intel . 2004. Intel ixp2xxx product line of network processors . Intel Corporation , Santa Clara , California. Intel. 2004. Intel ixp2xxx product line of network processors. Intel Corporation, Santa Clara, California."},{"key":"e_1_2_1_14_1","volume-title":"Proceedings of International Symposium on Microarchitecture. 361","author":"Kaxiras S.","unstructured":"Kaxiras , S. and Keramindas , G . 2003. Ipstash: a power-efficient memory architecture for ip-lookup . Proceedings of International Symposium on Microarchitecture. 361 . Kaxiras, S. and Keramindas, G. 2003. Ipstash: a power-efficient memory architecture for ip-lookup. Proceedings of International Symposium on Microarchitecture. 361."},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/972374.972393"},{"key":"e_1_2_1_16_1","volume-title":"Proceedings of International Symposium on High Performance Computer Architecture. 113","author":"Li H.","unstructured":"Li , H. , Bhunia , S. , Chen , Y. , Vijaykumar , T. , and Roy , K . 2003. Deterministic clock gating for microprocessor power reduction . In Proceedings of International Symposium on High Performance Computer Architecture. 113 . Li, H., Bhunia, S., Chen, Y., Vijaykumar, T., and Roy, K. 2003. Deterministic clock gating for microprocessor power reduction. In Proceedings of International Symposium on High Performance Computer Architecture. 113."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.859560"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2004.52"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.1"},{"key":"e_1_2_1_20_1","volume-title":"Proceedings of International Conference on Computer Aided Design. 39","author":"Memik G.","unstructured":"Memik , G. , Mangione-Smith , W. H. , and Hu , W . 2001. Netbench: A benchmarking suite for network processors . In Proceedings of International Conference on Computer Aided Design. 39 . Memik, G., Mangione-Smith, W. H., and Hu, W. 2001. Netbench: A benchmarking suite for network processors. In Proceedings of International Conference on Computer Aided Design. 39."},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/581630.581647"},{"key":"e_1_2_1_22_1","unstructured":"National Laboratory for Applied Network Research. The nlanr measurement and network analysis. National Laboratory for Applied Network Research (http:\/\/www.nlanr.net\/).  National Laboratory for Applied Network Research. The nlanr measurement and network analysis. National Laboratory for Applied Network Research (http:\/\/www.nlanr.net\/)."},{"key":"e_1_2_1_23_1","volume-title":"Proceedings of IEEE INFOCOM.","author":"Papagiannaki D.","unstructured":"Papagiannaki , D. , Taft , N. , Zhang , Z. , and Diot , C . 2003. Long-term forecasting of internet backbone traffic: Observations and initial models . In Proceedings of IEEE INFOCOM. Papagiannaki, D., Taft, N., Zhang, Z., and Diot, C. 2003. Long-term forecasting of internet backbone traffic: Observations and initial models. In Proceedings of IEEE INFOCOM."},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/344166.344526"},{"key":"e_1_2_1_25_1","volume-title":"International technology roadmap for semiconductors","author":"Semiconductor Industry Association","unstructured":"Semiconductor Industry Association . 2001. International technology roadmap for semiconductors . Semiconductor Industry Association , San Jose, CA . Semiconductor Industry Association. 2001. International technology roadmap for semiconductors. Semiconductor Industry Association, San Jose, CA."},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859652"},{"key":"e_1_2_1_27_1","unstructured":"Shim C. Xie L. Zhang B. and Sloane C. 2003. How delay and packet loss impact voice quality in voip. Qovia Inc. Fredereck MD.  Shim C. Xie L. Zhang B. and Sloane C. 2003. How delay and packet loss impact voice quality in voip. Qovia Inc. Fredereck MD."},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/502034.502056"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.486080"},{"key":"e_1_2_1_30_1","volume-title":"Symposium on VLSI Circuits Digest of Techical Papers, 69--70","author":"Thompson S.","unstructured":"Thompson , S. , Young , I. , Greason , J. , and Bohr , M . 1997. Dual threshold voltages and substrate bias: keys to high performance, low-power, 0.1 &mu;m logic designs . Symposium on VLSI Circuits Digest of Techical Papers, 69--70 . Thompson, S., Young, I., Greason, J., and Bohr, M. 1997. Dual threshold voltages and substrate bias: keys to high performance, low-power, 0.1 &mu;m logic designs. Symposium on VLSI Circuits Digest of Techical Papers, 69--70."},{"key":"e_1_2_1_31_1","volume-title":"Symposium on VLSI Circuits Digest of Techical Papers, 218--219","author":"Tschanz J.","unstructured":"Tschanz , J. , Ye , Y. , Wei , L. , Govindarajulu , V. , Borkar , N. , Burns , B. , Karnik , T. , Borkar , S. , and De , V . 2002. Design optimizations of a high-performance microprocessor using combinations of dual-vt allocation and transistor sizing . Symposium on VLSI Circuits Digest of Techical Papers, 218--219 . Tschanz, J., Ye, Y., Wei, L., Govindarajulu, V., Borkar, N., Burns, B., Karnik, T., Borkar, S., and De, V. 2002. Design optimizations of a high-performance microprocessor using combinations of dual-vt allocation and transistor sizing. Symposium on VLSI Circuits Digest of Techical Papers, 218--219."},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.818291"},{"key":"e_1_2_1_33_1","volume-title":"Proceedings of IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)","author":"Wolf T.","unstructured":"Wolf , T. and Franklin , M. A . 2000. CommBench - a telecommunications benchmark for network processors . In Proceedings of IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) . Austin, TX, 154--162. Wolf, T. and Franklin, M. A. 2000. CommBench - a telecommunications benchmark for network processors. In Proceedings of IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). Austin, TX, 154--162."},{"key":"e_1_2_1_34_1","volume-title":"Symposium on VLSI Circuits Digest of Techical Papers, 40--41","author":"Ye Y.","unstructured":"Ye , Y. , Borkar , S. , and De , V . 1998. A new technique for standby leakage reduction in high-performance circuits . Symposium on VLSI Circuits Digest of Techical Papers, 40--41 . Ye, Y., Borkar, S., and De, V. 1998. A new technique for standby leakage reduction in high-performance circuits. Symposium on VLSI Circuits Digest of Techical Papers, 40--41."},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1007\/11587514_6"}],"container-title":["ACM Transactions on Architecture and Code Optimization"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1216544.1216547","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,12,28]],"date-time":"2022-12-28T20:51:47Z","timestamp":1672260707000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1216544.1216547"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,3]]},"references-count":35,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2007,3]]}},"alternative-id":["10.1145\/1216544.1216547"],"URL":"https:\/\/doi.org\/10.1145\/1216544.1216547","relation":{},"ISSN":["1544-3566","1544-3973"],"issn-type":[{"value":"1544-3566","type":"print"},{"value":"1544-3973","type":"electronic"}],"subject":[],"published":{"date-parts":[[2007,3]]},"assertion":[{"value":"2007-03-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}