{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,23]],"date-time":"2025-04-23T05:27:44Z","timestamp":1745386064034},"publisher-location":"New York, NY, USA","reference-count":23,"publisher":"ACM","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2007,2,18]]},"DOI":"10.1145\/1216919.1216926","type":"proceedings-article","created":{"date-parts":[[2007,4,5]],"date-time":"2007-04-05T19:41:00Z","timestamp":1175802060000},"page":"45-52","update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":14,"title":["A versatile, low latency HyperTransport core"],"prefix":"10.1145","author":[{"given":"David","family":"Slogsnat","sequence":"first","affiliation":[{"name":"University of Mannheim, Mannheim, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alexander","family":"Giese","sequence":"additional","affiliation":[{"name":"University of Mannheim, Mannheim, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ulrich","family":"Br\u00fcning","sequence":"additional","affiliation":[{"name":"University of Mannheim, Mannheim, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2007,2,18]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Hypertransport Technology Consortium Hypertransport I\/O Link Specification Revision 2.00b Document #HTC20031217-0036-0009 2005.  Hypertransport Technology Consortium Hypertransport I\/O Link Specification Revision 2.00b Document #HTC20031217-0036-0009 2005."},{"key":"e_1_3_2_1_2_1","unstructured":"Hypertransport Technology Consortium Hypertransport I\/O Link Specification Revision 3.00 Document #HTC20051222-0046-0008 2006.  Hypertransport Technology Consortium Hypertransport I\/O Link Specification Revision 3.00 Document #HTC20051222-0046-0008 2006."},{"key":"e_1_3_2_1_3_1","unstructured":"Hypertransport Consortium HyperTransport EATX Mother-board\/Daughtercard Specification www.hypertransport.org 2004.  Hypertransport Consortium HyperTransport EATX Mother-board\/Daughtercard Specification www.hypertransport.org 2004."},{"key":"e_1_3_2_1_4_1","unstructured":"Hypertransport Consortium The Future of High Performance Computing: Direct Low Latency Peripheral-to-CPU Connections www.hypertransport.org November 2005.  Hypertransport Consortium The Future of High Performance Computing: Direct Low Latency Peripheral-to-CPU Connections www.hypertransport.org November 2005."},{"key":"e_1_3_2_1_5_1","unstructured":"Duncan Bees Brian Holden HyperTransport reduces delays in some applications EETimes 2004.  Duncan Bees Brian Holden HyperTransport reduces delays in some applications EETimes 2004."},{"key":"e_1_3_2_1_6_1","unstructured":"Advanced Micro Devices AMD BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD Opteron Processors #26094 Rev 3.3 2006.  Advanced Micro Devices AMD BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD Opteron Processors #26094 Rev 3.3 2006."},{"key":"e_1_3_2_1_7_1","unstructured":"Xilinx Corporation Virtex-4 User Guide Document ug070 v1.5 www.xilinx.com 2006.  Xilinx Corporation Virtex-4 User Guide Document ug070 v1.5 www.xilinx.com 2006."},{"key":"e_1_3_2_1_8_1","unstructured":"LinuxBIOS http:\/\/www.linuxbios.org  LinuxBIOS http:\/\/www.linuxbios.org"},{"key":"e_1_3_2_1_9_1","unstructured":"The HyperTransport Consortium http:\/\/www.hypertrans-port.org\/  The HyperTransport Consortium http:\/\/www.hypertrans-port.org\/"},{"key":"e_1_3_2_1_10_1","unstructured":"DRC RPU100-L60 Datasheet www.drccomputer.com\/pdfs\/DRC_RPU100_datasheet.pdf  DRC RPU100-L60 Datasheet www.drccomputer.com\/pdfs\/DRC_RPU100_datasheet.pdf"},{"key":"e_1_3_2_1_11_1","unstructured":"Celoxica RCHTX-XV4 Datasheet http:\/\/www.celoxica.com\/techlib\/files\/CEL-W06112119BY-517.pdf  Celoxica RCHTX-XV4 Datasheet http:\/\/www.celoxica.com\/techlib\/files\/CEL-W06112119BY-517.pdf"},{"key":"e_1_3_2_1_12_1","unstructured":"XtremeData XD1000 Product Brief http:\/\/www.xtremeda-tainc.com\/pdf\/XD1000_Brief.pdf  XtremeData XD1000 Product Brief http:\/\/www.xtremeda-tainc.com\/pdf\/XD1000_Brief.pdf"},{"key":"e_1_3_2_1_13_1","unstructured":"Center of Excellence on research in HyperTransport technology. Website: http:\/\/www.ra.informatik.uni-mannheim.de\/coe-ht\/  Center of Excellence on research in HyperTransport technology. Website: http:\/\/www.ra.informatik.uni-mannheim.de\/coe-ht\/"},{"key":"e_1_3_2_1_14_1","unstructured":"Kai Hwang Zhiwei Xu Scalable Parallel Computing 1st Edition McGraw-Hill 1998.  Kai Hwang Zhiwei Xu Scalable Parallel Computing 1st Edition McGraw-Hill 1998."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/CLUSTR.2000.888988"},{"volume-title":"IASTED Conference: Parallel and Distributed Computing and Networks (PDCN), Feb. 15 - 17","year":"2005","author":"Fr\u00f6ning Holger","key":"e_1_3_2_1_16_1"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1117201.1117211"},{"volume-title":"2nd Workshop on Architecture Research using FPGA Platforms","year":"2006","author":"Suh Taeweon","key":"e_1_3_2_1_18_1"},{"volume-title":"3rd annual FPGAWorld Conference","year":"2006","author":"Fr\u00f6ning Holger","key":"e_1_3_2_1_19_1"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/CONECT.2005.29"},{"key":"e_1_3_2_1_21_1","unstructured":"HyperTransport Lite Interface for Virtex-II FPGAs; XILINX; Document # 1-800-255-7778; 31.03.2004 http:\/\/www.xil-inx.com  HyperTransport Lite Interface for Virtex-II FPGAs; XILINX; Document # 1-800-255-7778; 31.03.2004 http:\/\/www.xil-inx.com"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/1117201.1117205"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/RSP.2005.6"}],"event":{"name":"FPGA07: ACM\/SIGDA International Symposium on Field Programmable Gate Arrays 2007","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"],"location":"Monterey California USA","acronym":"FPGA07"},"container-title":["Proceedings of the 2007 ACM\/SIGDA 15th international symposium on Field programmable gate arrays"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1216919.1216926","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,6]],"date-time":"2023-01-06T01:02:15Z","timestamp":1672966935000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1216919.1216926"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,2,18]]},"references-count":23,"alternative-id":["10.1145\/1216919.1216926","10.1145\/1216919"],"URL":"https:\/\/doi.org\/10.1145\/1216919.1216926","relation":{},"subject":[],"published":{"date-parts":[[2007,2,18]]},"assertion":[{"value":"2007-02-18","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}