{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T12:01:37Z","timestamp":1759147297929,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":12,"publisher":"ACM","license":[{"start":{"date-parts":[[2007,3,11]],"date-time":"2007-03-11T00:00:00Z","timestamp":1173571200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2007,3,11]]},"DOI":"10.1145\/1228784.1228800","type":"proceedings-article","created":{"date-parts":[[2007,4,5]],"date-time":"2007-04-05T19:41:00Z","timestamp":1175802060000},"page":"43-48","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["Robust wiring networks for DfY considering timing constraints"],"prefix":"10.1145","author":[{"given":"Philipp V.","family":"Panitz","sequence":"first","affiliation":[{"name":"University of Hannover, Hannover, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Markus","family":"Olbrich","sequence":"additional","affiliation":[{"name":"University of Hannover, Hannover, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Erich","family":"Barke","sequence":"additional","affiliation":[{"name":"University of Hannover, Hannover, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J\u00fcrgen","family":"Koehl","sequence":"additional","affiliation":[{"name":"IBM Deutschland Entwicklung GmbH, Boeblingen, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2007,3,11]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.148"},{"key":"e_1_3_2_1_2_1","volume-title":"IC Interconnect Analysis Kluwer Academic Publishers","author":"Celik M.","year":"2002","unstructured":"M. Celik , L. Pileggi , and A. Odabasioglu . IC Interconnect Analysis Kluwer Academic Publishers , 2002 . M. Celik, L. Pileggi, and A. Odabasioglu. IC Interconnect Analysis Kluwer Academic Publishers, 2002."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-0461-0","volume-title":"Interconnect Technology and Design for Gigascale Integration Kluwer Academic Piblishers","author":"Davis J. A.","year":"2003","unstructured":"J. A. Davis and J. D. Meindl . Interconnect Technology and Design for Gigascale Integration Kluwer Academic Piblishers , 2003 . J. A. Davis and J. D. Meindl. Interconnect Technology and Design for Gigascale Integration Kluwer Academic Piblishers, 2003."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/368640.368821"},{"key":"e_1_3_2_1_5_1","first-page":"617","volume-title":"Handbooks in Operations Research and Management Science","author":"Groetschel M.","year":"1995","unstructured":"M. Groetschel , C. L. Monma , and M. Stoer . Design of survivable networks . In Handbooks in Operations Research and Management Science , pages pp. 617 -- 672 , 1995 . M. Groetschel, C. L. Monma, and M. Stoer. Design of survivable networks. In Handbooks in Operations Research and Management Science, pages pp. 617--672, 1995."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.819426"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-2363-2"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.387740"},{"key":"e_1_3_2_1_9_1","first-page":"179","volume-title":"Proc. of the International Conference on Interated Circuit Design and Technology","author":"Panitz P.","year":"2006","unstructured":"P. Panitz , M. Olbrich , J. Koehl , and E. Barke . Application of global loops on ULSI routing for DfY . In Proc. of the International Conference on Interated Circuit Design and Technology , pages pp. 179 -- 182 , 2006 . P. Panitz, M. Olbrich, J. Koehl, and E. Barke. Application of global loops on ULSI routing for DfY. In Proc. of the International Conference on Interated Circuit Design and Technology, pages pp. 179--182, 2006."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.920683"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.45867"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.855928"}],"event":{"name":"GLSVLSI07: Great Lakes Symposium on VLSI 2007","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"],"location":"Stresa-Lago Maggiore Italy","acronym":"GLSVLSI07"},"container-title":["Proceedings of the 17th ACM Great Lakes symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1228784.1228800","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1228784.1228800","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T14:47:57Z","timestamp":1750258077000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1228784.1228800"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,3,11]]},"references-count":12,"alternative-id":["10.1145\/1228784.1228800","10.1145\/1228784"],"URL":"https:\/\/doi.org\/10.1145\/1228784.1228800","relation":{},"subject":[],"published":{"date-parts":[[2007,3,11]]},"assertion":[{"value":"2007-03-11","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}