{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:38:35Z","timestamp":1750307915160,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":18,"publisher":"ACM","license":[{"start":{"date-parts":[[2007,3,11]],"date-time":"2007-03-11T00:00:00Z","timestamp":1173571200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2007,3,11]]},"DOI":"10.1145\/1228784.1228804","type":"proceedings-article","created":{"date-parts":[[2007,4,5]],"date-time":"2007-04-05T19:41:00Z","timestamp":1175802060000},"page":"61-66","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Estimating path delay distribution considering coupling noise"],"prefix":"10.1145","author":[{"given":"Rajeshwary G.","family":"Tayade","sequence":"first","affiliation":[{"name":"University of Texas at Austin, Austin, TX"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vijay Kiran","family":"Kalyanam","sequence":"additional","affiliation":[{"name":"Advanced Micro Devices Inc., Austin, TX"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sani","family":"Nassif","sequence":"additional","affiliation":[{"name":"IBM, Austin, TX"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael","family":"Orshansky","sequence":"additional","affiliation":[{"name":"University of Texas at Austin, Austin, TX"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jacob","family":"Abraham","sequence":"additional","affiliation":[{"name":"University of Texas at Austin, Austin, TX"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2007,3,11]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337415"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337318"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.845079"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/1129601.1129720"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996665"},{"key":"e_1_3_2_1_6_1","volume-title":"Proc. of 4th Int. Symposium of Quality Electronic Design (ISQED)","author":"Agarwal K.","year":"2003","unstructured":"K. Agarwal , T. Sato , Y. Cao , D. Slyvester , and C. Hu , Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis , Proc. of 4th Int. Symposium of Quality Electronic Design (ISQED) , 2003 . K. Agarwal, T.Sato, Y.Cao, D.Slyvester, and C.Hu, Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis, Proc. of 4th Int. Symposium of Quality Electronic Design (ISQED), 2003."},{"key":"e_1_3_2_1_7_1","volume-title":"Proc. of 5th Int. Symposium of Quality Electronic Design (ISQED)","author":"Kulkarni M.","year":"2004","unstructured":"M. Kulkarni , T. Chen , A Sensitivity Based Approach to Analyzing Signal Delay Uncertainty of Coupled Interconnects , Proc. of 5th Int. Symposium of Quality Electronic Design (ISQED) , 2004 . M. Kulkarni, T. Chen, A Sensitivity Based Approach to Analyzing Signal Delay Uncertainty of Coupled Interconnects, Proc. of 5th Int. Symposium of Quality Electronic Design (ISQED), 2004."},{"key":"e_1_3_2_1_8_1","volume-title":"New Challenges in Delay Testing of Nanometer Multigigahertz Designs","author":"Mak T.M.","year":"2004","unstructured":"T.M. Mak , A. Kristic , K-T. Cheng , L-C. Wang , New Challenges in Delay Testing of Nanometer Multigigahertz Designs , IEEE CASS , 2004 . T.M. Mak, A. Kristic, K-T. Cheng, L-C. Wang, New Challenges in Delay Testing of Nanometer Multigigahertz Designs, IEEE CASS, 2004."},{"key":"e_1_3_2_1_9_1","volume-title":"ISQED","author":"Gattiker A.","year":"2001","unstructured":"A. Gattiker , S. Nassif , R. Dinakar , C. Long , Timing Yield Estimation from Static Timing Analysis , ISQED 2001 . A. Gattiker, S. Nassif, R. Dinakar, C. Long, Timing Yield Estimation from Static Timing Analysis, ISQED 2001."},{"key":"e_1_3_2_1_10_1","volume-title":"Automatic Generation for Critical-Path Tests for a Partial-Scan Microprocessor,ICCD","author":"Grodstein J.","year":"2003","unstructured":"J. Grodstein , D. Bhavasar , V. Bettada , R. Davies , Automatic Generation for Critical-Path Tests for a Partial-Scan Microprocessor,ICCD , 2003 . J. Grodstein, D. Bhavasar, V. Bettada, R. Davies, Automatic Generation for Critical-Path Tests for a Partial-Scan Microprocessor,ICCD, 2003."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379043"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1214\/aos\/1176347963"},{"key":"e_1_3_2_1_13_1","first-page":"229","volume-title":"An Effective Capacitance Based Delay Metric for RC Interconnect Proc. of Int. Conf. on Computer Aided Design","author":"Kashyap C.V.","year":"2000","unstructured":"C.V. Kashyap , C.J. Alpert , A. Devgan , An Effective Capacitance Based Delay Metric for RC Interconnect Proc. of Int. Conf. on Computer Aided Design , pp. 229 -- 234 , San Jose, CA , Nov 2000 . C.V. Kashyap, C.J. Alpert, A. Devgan, An Effective Capacitance Based Delay Metric for RC Interconnect Proc. of Int. Conf. on Computer Aided Design, pp. 229--234, San Jose, CA, Nov 2000."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/332357.332377"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.835137"},{"key":"e_1_3_2_1_16_1","first-page":"335","volume-title":"IEEE Intl. Symposium on Defect and Fault Tolerance in VLSI Systems","author":"Variyam P.","year":"1998","unstructured":"P. Variyam , A. Chatterjee , Specification-Driven Test Design for Analog Circuits , IEEE Intl. Symposium on Defect and Fault Tolerance in VLSI Systems , pp. 335 -- 340 , Nov. 1998 . P. Variyam, A.Chatterjee, Specification-Driven Test Design for Analog Circuits, IEEE Intl. Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 335--340, Nov. 1998."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996663"},{"key":"e_1_3_2_1_18_1","volume-title":"Proc. CMP-MIC","author":"Stine B.","year":"1997","unstructured":"B. Stine , A Closed-Form Analytic Modek for ILD Thickness Variation in CMP Processes , Proc. CMP-MIC , Santa Clara, CA , Feb , 1997 . B. Stine, et al. A Closed-Form Analytic Modek for ILD Thickness Variation in CMP Processes, Proc. CMP-MIC, Santa Clara, CA, Feb, 1997."}],"event":{"name":"GLSVLSI07: Great Lakes Symposium on VLSI 2007","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"],"location":"Stresa-Lago Maggiore Italy","acronym":"GLSVLSI07"},"container-title":["Proceedings of the 17th ACM Great Lakes symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1228784.1228804","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1228784.1228804","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T14:47:57Z","timestamp":1750258077000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1228784.1228804"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,3,11]]},"references-count":18,"alternative-id":["10.1145\/1228784.1228804","10.1145\/1228784"],"URL":"https:\/\/doi.org\/10.1145\/1228784.1228804","relation":{},"subject":[],"published":{"date-parts":[[2007,3,11]]},"assertion":[{"value":"2007-03-11","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}