{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:38:28Z","timestamp":1750307908474,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":24,"publisher":"ACM","license":[{"start":{"date-parts":[[2007,3,11]],"date-time":"2007-03-11T00:00:00Z","timestamp":1173571200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2007,3,11]]},"DOI":"10.1145\/1228784.1228853","type":"proceedings-article","created":{"date-parts":[[2007,4,5]],"date-time":"2007-04-05T19:41:00Z","timestamp":1175802060000},"page":"275-280","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["Analyzing and modeling process balance for sub-threshold circuit design"],"prefix":"10.1145","author":[{"given":"Joseph F.","family":"Ryan","sequence":"first","affiliation":[{"name":"University of Virginia, Charlottesville, VA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jiajing","family":"Wang","sequence":"additional","affiliation":[{"name":"University of Virginia, Charlottesville, VA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Benton H.","family":"Calhoun","sequence":"additional","affiliation":[{"name":"University of Virginia, Charlottesville, VA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2007,3,11]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"9","article-title":"Scaling, Power, and the Future of CMOS","author":"Horowitz M.","year":"2005","unstructured":"M. Horowitz , , \" Scaling, Power, and the Future of CMOS ,\" IEDM , pp. 9 -- 15 , December 2005 . M. Horowitz, et al., \"Scaling, Power, and the Future of CMOS,\" IEDM, pp. 9--15, December 2005.","journal-title":"IEDM"},{"key":"e_1_3_2_1_2_1","volume-title":"September","author":"Vittoz E.","year":"1976","unstructured":"E. Vittoz and J. Fellrath , \" New Analog CMOS IC's Based on Weak Inversion Operation,\" ESSCIRC , September 1976 . E. Vittoz and J. Fellrath, \"New Analog CMOS IC's Based on Weak Inversion Operation,\" ESSCIRC, September 1976."},{"volume-title":"Ion-Implanted Complementary MOS Transistors&,\" JSSC","author":"Swanson R. M.","key":"e_1_3_2_1_3_1","unstructured":"R. M. Swanson and J. D. Meindl , \" Ion-Implanted Complementary MOS Transistors&,\" JSSC , vol. 7 , no. 2, April. 1972. R. M. Swanson and J. D. Meindl, \"Ion-Implanted Complementary MOS Transistors&,\" JSSC, vol. 7, no. 2, April. 1972."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/313817.313874"},{"key":"e_1_3_2_1_5_1","first-page":"7","article-title":"Optimal Supply and Threshold Scaling for Sub-threshold CMOS Circuits","author":"Wang A.","year":"2002","unstructured":"A. Wang , A. Chandrakasan , and S. Kosonocky , \" Optimal Supply and Threshold Scaling for Sub-threshold CMOS Circuits ,\" Symposium on VLSI , pp. 7 -- 11 , April 2002 . A. Wang, A. Chandrakasan, and S. Kosonocky, \"Optimal Supply and Threshold Scaling for Sub-threshold CMOS Circuits,\" Symposium on VLSI, pp. 7--11, April 2002.","journal-title":"Symposium on VLSI"},{"issue":"9","key":"e_1_3_2_1_6_1","first-page":"1778","article-title":"Modeling and Sizing for Minimum Energy Operation in Sub-threshold Circuits","volume":"40","author":"Calhoun B.H.","year":"2005","unstructured":"B.H. Calhoun , , \" Modeling and Sizing for Minimum Energy Operation in Sub-threshold Circuits ,\" JSSC , Vol. 40 , No. 9 , pp. 1778 -- 1786 , September 2005 . B.H. Calhoun, et al., \"Modeling and Sizing for Minimum Energy Operation in Sub-threshold Circuits,\" JSSC, Vol. 40, No. 9, pp. 1778--1786, September 2005.","journal-title":"JSSC"},{"key":"e_1_3_2_1_7_1","first-page":"292","article-title":"A 180mV FFT Processor Using Sub-threshold Circuit Techniques","author":"Wang A.","year":"2004","unstructured":"A. Wang and A. Chandrakasan , \" A 180mV FFT Processor Using Sub-threshold Circuit Techniques ,\" ISSCC , pp. 292 -- 293 , 2004 . A. Wang and A. Chandrakasan, \"A 180mV FFT Processor Using Sub-threshold Circuit Techniques,\" ISSCC, pp. 292--293, 2004.","journal-title":"ISSCC"},{"key":"e_1_3_2_1_8_1","first-page":"628","article-title":"A 256kb Sub-threshold SRAM in 65nm CMOS","author":"Calhoun B.H.","year":"2006","unstructured":"B.H. Calhoun and A. Chandrakasan , \" A 256kb Sub-threshold SRAM in 65nm CMOS ,\" ISSCC , pp. 628 -- 629 , 2006 . B.H. Calhoun and A. Chandrakasan, \"A 256kb Sub-threshold SRAM in 65nm CMOS,\" ISSCC, pp. 628--629, 2006.","journal-title":"ISSCC"},{"key":"e_1_3_2_1_9_1","volume-title":"A 2.60pJ\/Inst Subthreshold Sensor Processor for Optimal Energy Efficiency,\" VLSI Ckts Symp","author":"Zhai B.","year":"2006","unstructured":"B. Zhai , , \" A 2.60pJ\/Inst Subthreshold Sensor Processor for Optimal Energy Efficiency,\" VLSI Ckts Symp , 2006 . B. Zhai, et al., \"A 2.60pJ\/Inst Subthreshold Sensor Processor for Optimal Energy Efficiency,\" VLSI Ckts Symp, 2006."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1077603.1077610"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1013235.1013266"},{"key":"e_1_3_2_1_12_1","volume-title":"No.","author":"Chen J.","year":"2006","unstructured":"J. Chen , An Ultra-Low-Power Memory with a Subthreshold Power Supply Voltage,\" JSSC, Vol. 41 , No. 10, Oct 2006 . J. Chen, et al., \"An Ultra-Low-Power Memory with a Subthreshold Power Supply Voltage,\" JSSC, Vol. 41, No. 10, Oct 2006."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1165573.1165578"},{"key":"e_1_3_2_1_14_1","volume-title":"New Paradigm of Predictive MOSFET and Interconnect Modeling for Early Circuit Design,\" CICC","author":"Cao Y.","year":"2000","unstructured":"Y. Cao , , \" New Paradigm of Predictive MOSFET and Interconnect Modeling for Early Circuit Design,\" CICC , 2000 . Y. Cao, et al., \"New Paradigm of Predictive MOSFET and Interconnect Modeling for Early Circuit Design,\" CICC, 2000."},{"key":"e_1_3_2_1_15_1","unstructured":"http:\/\/www.eas.asu.edu\/~ptm (November 19 2006).  http:\/\/www.eas.asu.edu\/~ptm (November 19 2006)."},{"volume-title":"Ultra-Dynamic Voltage Scaling (UDVS)..\" JSSC","author":"Calhoun B.H.","key":"e_1_3_2_1_16_1","unstructured":"B.H. Calhoun and A. Chandrakasan , \" Ultra-Dynamic Voltage Scaling (UDVS)..\" JSSC , Vol. 41 , No. 1, 2006. B.H. Calhoun and A. Chandrakasan, \"Ultra-Dynamic Voltage Scaling (UDVS)..\" JSSC, Vol. 41, No. 1, 2006."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF00896619"},{"key":"e_1_3_2_1_18_1","first-page":"22","volume-title":"Device Research Conference","author":"Bryant A.","year":"2001","unstructured":"A. Bryant , Low-Power CMOS at Vdd=4kT\/q,\" Device Research Conference , pp. 22 -- 23 , June 2001 . A. Bryant, et al., \"Low-Power CMOS at Vdd=4kT\/q,\" Device Research Conference, pp. 22--23, June 2001."},{"key":"e_1_3_2_1_19_1","volume-title":"CRC Press","author":"Vittoz E.","year":"2005","unstructured":"E. Vittoz , \" Weak Inversion for Ultimate Low-Power Logic ,\" in Low-Power Electronics Design , C. Piguet , Ed. CRC Press , 2005 . E. Vittoz, \"Weak Inversion for Ultimate Low-Power Logic,\" in Low-Power Electronics Design, C. Piguet, Ed. CRC Press, 2005."},{"key":"e_1_3_2_1_20_1","volume-title":"An 8-8 Sub-threshold Digital CMOS Carry Save Array Multiplier,\" ESSCIRC","author":"Paul B. C.","year":"2001","unstructured":"B. C. Paul , H., Soeleman, and K. Roy , \" An 8-8 Sub-threshold Digital CMOS Carry Save Array Multiplier,\" ESSCIRC , 2001 . B. C. Paul, H., Soeleman, and K. Roy, \"An 8-8 Sub-threshold Digital CMOS Carry Save Array Multiplier,\" ESSCIRC, 2001."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1165573.1165603"},{"key":"e_1_3_2_1_22_1","volume-title":"Sub-threshold Design for Ultra Low-Power Systems","author":"Wang A.","year":"2006","unstructured":"A. Wang , B. Calhoun , and A. Chandrakasan , Sub-threshold Design for Ultra Low-Power Systems , Springer , 2006 . A. Wang, B. Calhoun, and A. Chandrakasan, Sub-threshold Design for Ultra Low-Power Systems, Springer, 2006."},{"volume-title":"Static Noise Margin Variation for Subthreshold SRAM in 65nm CMOS,\" JSSC","author":"Calhoun B.H.","key":"e_1_3_2_1_23_1","unstructured":"B.H. Calhoun , \" Static Noise Margin Variation for Subthreshold SRAM in 65nm CMOS,\" JSSC , Vol. 41 , No. 7, July 2006. B.H. Calhoun et al., \"Static Noise Margin Variation for Subthreshold SRAM in 65nm CMOS,\" JSSC, Vol. 41, No. 7, July 2006."},{"key":"e_1_3_2_1_24_1","first-page":"55","article-title":"SRAM Leakage Suppression by Minimizing Standby Supply Voltage","author":"Qin H.","year":"2004","unstructured":"H. Qin , , \" SRAM Leakage Suppression by Minimizing Standby Supply Voltage ,\" ISQED , pp. 55 -- 60 , 2004 . H. Qin, et al., \"SRAM Leakage Suppression by Minimizing Standby Supply Voltage,\" ISQED, pp. 55--60, 2004.","journal-title":"ISQED"}],"event":{"name":"GLSVLSI07: Great Lakes Symposium on VLSI 2007","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation"],"location":"Stresa-Lago Maggiore Italy","acronym":"GLSVLSI07"},"container-title":["Proceedings of the 17th ACM Great Lakes symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1228784.1228853","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1228784.1228853","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T14:47:46Z","timestamp":1750258066000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1228784.1228853"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,3,11]]},"references-count":24,"alternative-id":["10.1145\/1228784.1228853","10.1145\/1228784"],"URL":"https:\/\/doi.org\/10.1145\/1228784.1228853","relation":{},"subject":[],"published":{"date-parts":[[2007,3,11]]},"assertion":[{"value":"2007-03-11","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}